Table Of ContentMicroprocessing and Microprogramming 34 (1992) 255-257
North-Holland
Author index to volume 34 (1992)
Acevedo-Sotoca, M., see Lopez-Aligue, F.J. 247 problem in client-server model
Adan-Coello, J.M. and M. Ferreira Magalhaes, STER’S Cseke, |., see Ambrézy, Gy.
multilevel programming model for distributed hard
real-time systems
Dabrowski, J., Efficient timing verification via mixed-
Alexandres, S., see Carazo, J.
mode technique
Alexandres, S., see Moran, J. 85
Dasi, P.K., see Pramanik, P.
Ambrézy, Gy., |. Cseke, Z. Fazekas and S. Zold, ARGUS
Deliyannis, T., see Horianopoulos, S.L.
— A PC based image processing workstation, its
Dorigo, M., Using transputers to increase speed and
software and some application examples
flexibility of genetics-based machine learning systems
Annunziata, M., S. Calabrese and R. Lorello, SIPA: An
activity-planning system 23
Elovici, Y., see Azaria, H.
Aude, J.S., see Silva, G.P.
Avellana, N., see Carrabina, J. 89
Azaria, H., Y. Elovici and R.D. Hersch, Multiple interfaces Fagerstrom, J., see Ringstrom, J.
message passing system for transputer network 237 Fan, X., Queue-based primitives for a multithreaded
architecture
Fay, D.Q.M., see Pramanik, P.
Bailey, N., A. Purvis, P.D. Manning and |. Bowler, Some
Fazekas, Z., see Ambrézy, Gy.
observations on hierarchical, multiple-instruction-
Fernandez, E.S.T., see Barbosa, F.M.B.
multiple-data computers
Fernandez, E.S.T., C.F. Bornstein and M.D. Pereira,
Bandyopadhyay, A.K., see Pramanik, P.
Parallel code generation for super-scalar architectures
Bango, Gy., M. Gardos, J. Miskolczi, |. Szabo and I.
Fernandez, F., see Polo, V.
Renyi, Design concepts and realization of the
Ferreira Magalhaes, M., see Adan-Coello, J.M.
hardware structure of ARGUS image processing
Flanigan, J., see McConnell, R.
workstation 207
Fonio, H.-R. and A. Pawlak, Rule-based synthesis using
Barbosa, F.M.B. and E.S.T. Fernandez, Dispatching
ADTs and term rewriting
simultaneous instructions 227
Fritzson, P., see Ringstrom, J.
Biswas, P., see Su, S.C. 187
Fritzson, P., see Kroha, P.
Blazek, Z. and |. Jelinek, Multiprocessor monitoring
system 163
Bornstein, C.F., see Fernandez, E.S.T. 215 Gandelli, A. and V. Piuri, A highly-parallel system for
Bowler, |., see Bailey, N. 211 real-time electronic measurements
Brezany, P. and V. Sipkova, Compiling a vector and array Gardos, M., see Bango, Gy.
Garrido, F., see Carrabina, J.
processing language for an associative processor 171
Britton, C., see Buchanan, M. 19 Gianuzzi, V., see Clematis, A.
Buchanan, M. and C. Britton, Formal specification and Gémez, L., A. Hernandez and S. Nunez, Timing model for
SDCEFL digital circuits
object-oriented design 19
Goutis, C.E., see Horianopoulos, S.L.
Calabrese, S., see Annunziata, M. 23
Calderon, J.C., see Carrabina, J. 89 Haggenmiuller, R., see Pfeiffer, M.
Carazo, J., S. Alexandres and J. Moran, Speech Havinga, P.J.M., see Smit, G.J.M.
recognizer optimization and real-time implementation Hermida, R., see Mozos, D.
on a multitransputer array Hernandez, A., see G6mez, L.
Carrabina, J., J.C. Calderon, F. Lisa, C. Perez, F. Garrido, Hersch, R.D., see Azaria, H.
N. Avellana and E. Valderrama, Digital neural network Holton, D.R.W., see McKeever, J.D.M.
system based in new concepts on the recall phase Horianopoulos, S.L., D.£. Metafas, C.E. Goutis and
dynamics T. Deliyannis, A VLSI synthesis for complementary
Clematis, A. and V. Gianuzzi, The conversation deadlock output Delta Modulation FIR filters
256 Author index to volume 34 (1992)
Janecek, J., POLLUX: A language for distributed system delegation and inheritance in object oriented
programming 33 languages
Jansen, P.G., see Smit, G.J.M. 59 Nunez, S., see Gomez, L.
Jelinek, |., see Blazek, Z.
Jereb, B. and L. Pipan, Measuring parallelism in Ojstersek, M. and V. Zumer, Improving a time critical task
algorithms execution time using an IPRESPS 197
Kim, Yoo S. and Song C. Moon, Update synchronization Pawlak, A., see Fonio, H.-R. 81
pursuing site autonomy in heterogeneous distributed Pereira, M.D., see Fernandez, E.S.T.
databases 41 Perez, C., see Carrabina, J. 89
Kokkinidis, P.A. and C. Metaxaki-Kossionidou, An Pfeiffer, M. and R. Haggenmuller, System engineering
adaptive improvement of an image compression with DOMINO and GRAPES
technique Piechowka, M. and S. Szejko, An object-oriented kernel
Kroha, P. and P. Fritzson, Software features of an for distributed simulation of concurrent systems
extended single instruction machine Pipan, L., see Jereb, B.
Kroon, J.G.M., The software development environment Piuri, V. and R. Stefanelli, Fault-tolerant techniques for
at Rijkswaterstaat VLSI tree structures
Piuri, V., see Gandelli, A.
Lecordier, R. and P. Martin, Data flow processors for Polo, V., F. Fernandez and A. Sanchez, Parallel
automated visual inspection implementation of local averaging for image
Lisa, F., see Carrabina, J. processing
Lopez-Aligue, F.J., M. Acevedo-Sotoca and Pramanik, P., P.K. Dasi, A.K. Bandyopadhyay and
A. Jaramillo- Moran, Multimicrocomputer D.Q.M. Fay, Avoidance of deadlock in loop structures
implementation of three-dimensional neural networks 247 —a two process solution 103
Lorello, R., see Annunziata, M. 23 Purvis, A., see Bailey, N. 211
Maeng, S., see Ryu, K. Randon, E., P. Sanchez and E. Villar, ESP, a structure
Manning, P.D., see Bailey, N. synthesis program
Martin, P., see Lecordier, R. 37 Rea, S.A., see Milligan, P. 73
Mayer-Lindenberg, F., Interactive software development Rea, S.A., see Milligan, P. 77
for complex embedded systems 179 Renyi, |., see Bango, Gy. 207
McConnell, R. and J. Flanigan, A simple switching Ringstrom, J., P. Fritzson and J. Fagerstrom, FREDULA:
system for transputer links 243 A multi- paradigm parallel programming and
McConnell, R.K., see Milligan, P. 73 debugging environment
McConnell, R.K., see Milligan, P. 77 Ryu, K. and S. Maeng, Specifying and inheriting
McKeag, R.M., see McKeever, J.D.M. concurrent objects
McKeever, J.D.M., D.R.W. Holton and R.M. McKeag,
Using transputers in a robot programming and control Sage, P.P., see Milligan, P.
system 117 Sampsonidis, D. and Zamani, M., An image analysis
Metafas, D.E., see Horianopoulos, S.L. 139 system for automatic measurements in solid state
Metaxaki-Kossionidou, C., see Kokkinidis, P.A. 231 nuclear track detectors
Milligan, P., R.K. McConnell, S.A. Rea and P.P. Sage, Sanchez, P., see Randon, E.
FortPort: An environment for the development of Sanchez, A., see Polo, V.
parallel Fortran programs Sandoval, F., see Vico, F.J.
Milligan, P., S.A. Rea, R.K. McConnell and Septién, J., see Mozos, D. 93
H.R.J. Walters, Parallel collocation modelling: A case Serbedzija, N.B., Parallel programming on a PC —-Acase
study in developing efficient parallel codes 77 study 121
Miskolczi, J., see Bango, Gy. Silva, G.P. and J.S. Aude, Evaluation of a SPARC
Moon, Song C., see Yoon, Yong I. 63 architecture with Harvard bus and branch target cache 157
Moon, Song C., see Kim, Yoo S. 41 Sipkova, V., see Brezany, P. 171
Moran, J. and S. Alexandres, A comparison of some Smai, A.-H., see Wu, H. 175
processor farm architectures 85 Smit, G.J.M., P.J.M. Havinga and P.G. Jansen, On the
Moran, J., see Carazo, J. 215 design of a dynamic reconfigurable network switch 59
Mozos, D., J. Septién, F. Tirado and R. Hermida, Design Stefanelli, R., see Piuri, V. 97
control in a high level synthesis system 93 Su, S.C. and P. Biswas, A memory-mapped
interprocessor communication architecture using FIFO —
Nieddu, P., Aunifying approach to clientship, RAMs 187
Author index to volume 34 (1992)
Svéda, M., Microcontroller software engineering 11 Villar, E., see Randon, E.
Szabo, |., see Bango, Gy.
Szejko, S., see Piechowka, M. Walters, H.R.J., see Milligan, P.
Withagen, W.J., see van Wezenbeek, A.M.
Thorelli, L.-E., see Wu, H. Wu, H., L.-E. Thorelli and A.-H. Smai, Flow control for
Tirado, F., see Mozos, D. efficient realization of the EDA model
Tudruj, M., Multi-layer reconfigurable transputer
systems with distributed control of link connections
Yoon, Yong |. and Song C. Moon, Reliable transaction
processing for real-time distributed database system
Valderrama, E., see Carrabina, J.
van Wezenbeek, A.M. and W.J. Withagen, Adaptive
window working set replacement policies Zamani, M., see Sampsonidis, D.
Vico, F.J. and F. Sandoval, Neural networks definition Zold, S., see Ambrézy, Gy.
algorithm Zumer, V., see Ojstersek, M.
Microprocessing and Microprogramming 34 (1992) 259-260
North-Holland
Subject index to volume 34 (1992)
Activity planning FIFO RAM
Adaptive method Flow control algorithm
Adaptive window policy Formal specification
ADTs and term rewriting 4GL programming language
ARGUS image processing workstation
ARGUS system Genetics-based machine learning
Associative processor GRAPES
Asynchronous process communication
Automated visual inspection
Harvard bus
Automatic measurement
Heterogeneous distributed databases
High level synthesis system
Branch target cache Highly-parallel system
CAD of VLSI ICs
Image analysis system
Case tools
Image compression
Clientship
Image preprocessing
Complex embedded systems
Image processing
Concurrent objects
Image processing workstation
Concurrent programs
Implementation on transputers
Concurrent systems Inheritance
Configuration
Integrated commit protocol
inter-processor communication
Database techniques Interactive software development
Dataflow processors Interconnection network
Deadlock Interference problem
Debugging environment
Degree of connection
Kautz graphs
Degree of simultaneousness
Delegation
Load balance
Delta modulation
Local averaging
Deserter process problem
Loop structures
Design automation
Design control
Man-power planning
Digital circuits
Memory management simulation program
Digital neural network system
Message-passing system
Digital signal processing
Microcontroller software engineering
Dispatching
Distributed control Mixed-mode technique
Monitoring system
Distributed hard real-time systems
Multi-layer reconfigurable transputer systems
Distributed simulation
Multiple-instruction multiple-data computers
Distributed systems
Multiple interfaces message passing system
Distributed transaction processing
Multiprocessor
DOMINO
Multithreaded architecture
Dusty deck codes
Fault-tolerance Network switch
Field programmable gate array Neural network definition
260 Subject index to volume 34 (1992)
OBJ programming language 19 RT synthesis
Object oriented analysis Rule-based synthesis
Object-oriented kernel
Object oriented languages Silicon compilation
Simultaneous instructions
Parallel algorithms Single instruction computer
Parallel code generation Site autonomy
Parallel codes SPARC architecture
Parallel collocation modelling Speech recognition
Parallel Fortran programs Static partitioning
Parallel genetic algorithms STER environment
Parallel implementation Super-scalar architectures
Parallel processing Switching system
Parallel programming System engineering
Parallel programming language
PREDULA Teaching robot
Processors farm Three-dimensional neural networks
Programmable architecture 3GL programming language
Pruning Time critical task execution
Time verification
Queue-based primitives Timing model
Transputer 85,117,211,
Real-time Transputer links
Real-time electronic measurements
Recall phase dynamics VLSI synthesis tool
Remote procedure call VLSI tree structures
