Table Of Content

Microprocessing and Microprogramming 32 (1991) 873-878 873 North-Holland AUTHOR INDEX Aguado, M.J., J.L. Conesa, E. de la Torre and J. Bronstein, G.P., see Aude, J.S. 45 Uceda, A new approach on fault list handling for Buananno, G., see Hadjinicolaeu, M. 675 faster fault elimination and direct test vector Buddefeld, J., K.E. Grosspietsch, B.J. Hosticka, R. generation 853 Klinke and G. Wagner, An intelligent sensor 447 Alenius, S., see Neejarvi, J. integrated preprocessing facility for neural net- Alippi, C., The determination of angular values and works 335 parameters in flat surfaces: from the Buonanno, G., F. Lombardi, D. Sciuto and Y.-N. mathematical approach to the CORDIC Shen, Multiple stuck-at faults detection in architecture 349 CMOS combinational gates 775 Alippi, C., see Refenes, A.N. 437 Burgess, M., see Hadjinicolaeu, M. 675 Ancona, M., G. Nani and M. Paci, An object oriented approach to data persistence 263 Calvo Torre, F., From a high level description of an Anido, M.L., Improving the division instruction of IC to silicium: don’t loose design intent 413 application-specific RISCs 13 Cappello, F., see Bechennec, J.-L. 171 Antola, A. and F. Distante, DFG: a graph based Carballo, P.P., see Eshraghian, K. 75 approach for algorithmic flow driven architecture Carpenter, G.F. and A.M. Tyrrell, Software fault synthesis 683 tolerance in concurrent systems: conversation Antoniazzi, S. and M. Mastretti, An architectural placement using CSP 373 design support environment for high-performance Cavalooro, P., see Hadjinicolaeu, M. 675 digital systems 315 Chariton, C., P. Leng and M. Rivers, Object-oriented Aude, J.S., AJ.O. Cruz, A.C. Pacheco Jr,. A.M. modelling in digital circuit CAD Systems 93 Meslin, G. Bronstein, G.P. Azevedo, N.R. Figueira, Chen, R.J., see Tsai, S.R. 145 R.P. Azevedo and S.C. Oliveira, MULTIPLUS: a Chlamtac, |., A. Ganz and M.G. Kienzle, Control modular high-performance multiprocessor 45 policies for interconnected distributed systems via Auvergne, D., see Navarro, D. 645 an HIPPI switch 575 Ayguadé, E., see Cortadella, J. 199 Clematis, A. and V. Gianuzzi, Software fault tolerance Azevedo, G.P., see Aude, J.S. 45 in concurrent ADA programs 365 Azevedo, R.P., see Aude, J.S. 45 Compan, A., P. Debaud, V. Delorme, J.A. Francois, H. Mehrez and F. Pécheux, GAF: a portable Badia, R.M., see Cortadella, J. 199 standard-cell floating point adder generator using Balou, A.T. and A.N. Refenes, The design and the CXgen function library 637 implementation of VOOM: a parallel virtual Conesa, J.L., see Aguado, M.J. 853 object oriented machine 289 Cortadella, J.. R.M. Badia and E. Ayguadé, Barbosa, V.C., see Fernandes, E.S.T. 23 Scheduling in a continuous area-time design Barbosa, V.C., L.M. de A Drummond and ALL. space 199 Hellmuth, An integrated software environment for Cruz, A.J.O., see Aude, J.S. 45 large-scale Occam programming 393 Cruz, L., see Silva, V. 343 Bechennec, J.-L., F. Cappello and D. Etiemble, 3D Cu, X., K. Kuchcinski and Z. Peng, Testability hardware packages for parallel architectures 171 measure with reconvergent fanout analysis and its Bendens, L.P.M. and M.P.J. Stevens, Task level applications 835 behavioral hardware description 323 Berger Sabbatel, G. and A. Jemai, Prolog on a RISC: De A. Drummond, L.M., see Barbosa, V.C. 393 implementation and evaluation 497 De Boer, F., see Smit, G.J.M. 593 Bouaziz, S., E. Pissaloux, A. Mérigot and F. Devos, A De SA, L., see Silva, V. 343 communication mechanism and its implementa- De Souza, A.F., see Fernandes, E.S.T. 23 tion in the Multi-SIMD massively parallel machine Dal Cin, M., Fault tolerance for highly parallel SPHINX 39 computers 237 Brenner, E., J. Grabner, M. Moosburger, G. Otschko, Darlay, F., Detection of multiple stuck-on/stuck-open K. Schldgl, P. Seifter, J. Song, Ch. Steger faults by single faults test sets in MOS transistor and R. Weiss, Design and implementation of a networks 783 distributed real-time expertsystem for fault diag- De la Torre, E., see Aguado, M.J. 853 nosis in modular manufacturing systems 799 Debaud, P., see Compan, A. 637 874 Author index Delaney, T.A., see Sorensen, H. 489 Hadjinicolaeu, M., N. Burgess, D. Sciuto, G. Buananno, P. Cavalooro and G. Zara, The Delaplace, F. and J.L. Giavitto, An efficient routing strategy to support process migration 153 PARTICIA testability analysis tool 675 Delattre, E., see Hemery, F. 137 Haeck, H.-G., F. Krohm and Y. Manoli, Data path Delorme, V., see Compan, A. 637 synthesis from a microcontroller instruction Deschacht, M., see Navarro, D. 645 set specification in MicroSyn 193 Devos, F., see Bouaziz, S. 39 Haris, R.L., see Mayger, E.M. 667 Diaz, M. V. E., see Fernandez, M.A.R. 401 Havinga, P.J.M., see Smit, G.J.M. 593 Distante, F., see Antola, A. 683 Hellmuth, A.H., see Barbosa, V.C. 393 Doettling, G., Data consistency in a multiprocessor Hellwagner, H., see Muller-Wipperfurth, T. 651 system with ‘store in’ cache concept 215 Hemery, F., D. Lazure, E. Delattre and J.-F. Mehaut, Dours-Senac, C., Temporal control improvement of An analysis of communication and multiprogram- Hidden Markov Models for automatic speech ming in the Helios operating system 137 recognition 549 Hermida, R., see Septién, J. 185 Downs, T., see Lakshmi Narasimhan, V. 243 Hinsen, H., see Hubner, U. 791 Dowsing, R.D. and R. Elliott, A higher level of Hofebauer, M., see Hubner, U. 791 behavioural specification: an example in Holding, J., see Sagoo, J.S. 111 interval temporal logic 517 Holte, R., see Zimmer, R. 691 Honka, H. and M. Kattilakoski, A simulation-based Eisele, V. and D. Schmitt-Landsiedel, Optimization system for testing real-time embedded software in and architectural evaluation of regular the host environment 127 combinatoric structures 69 Hosticka, B.J., see Buddefeld, J. 335 El-Kassas, S., Visual languages: their definition and Hsieh, W.S., see Huang, K.C. 281 applications in system development 383 Hsieh, W.S., see Yang, C.S. 583 Elliott, R., see Dowsing, R.D. 517 Hsieh, W.S., T.S. Nain, M.S. Yang, C.S. Lu, K.C. Erenyi, |. and J. Pongracz, Quality control in textile Huang, and J.R. Tseng, A fast method of industry via machine vision 807 protocol validation using reduced stable state Eshraghian, K., R. Sarmiento, P.P. Carballo and A. exploration technique 723 Nunez, Speed-area-power optimization for DCFL Hu, Y.-C., A. Verschueren and M.P.J. Stevens, Object and SDCFL class of logic using ring notation 75 oriented system analysis for VLSI 101 Etiemble, D., see Bechennec, J.-L. 171 Huang, K.C., W.S. Hsieh, C.S. Lu, M.S. Yang, T.S. Nain and |. Lin, Implementation and design of Fernandes, E.S.T., V.C. Barbosa, A.F. de Souza and PVD: an interactive protocol specification and N.Q. Vasconcelos, Micro-instruction placement by validation environment 281 simulated annealing 23 Huang, K.C., see Yang, C.S. 589 Fernandez, A., J.M. Llaberia, J.J. Navarro and M. Huang, K.C., see Hsieh, W.S. 723 Valeno-Gracia, Performance evaluation of Hubner, U., H. Hinsen, M. Hofebauer and H.T. transputer systems with linear algebra problems 825 Vierhaus, Mixed level test generation for high fault Fernandez, M.A.R., G.L. Serrano and M.V.E. Diaz, An coverage 791 integrated framework for the design of distributed Huis in 't Veld, R.J., Formalizing the design-trajectory programming environments 401 of sequential machines 531 Ferragut, L., R. Montenegro, G. Winter and A. Nufiez, Hwang, B.Y., B.W. Kim and S.C. Moon, Efficient Accurate extraction of interconnect capacitances access method for multi-dimensional complex by adaptive mixed F.E.M. 61 objects in spatial databases: BR tree 765 Figueira, N.R., see Aude, J.S. 45 Fischer, V., see Neejarvi, J. 447 Jansen, P.G., see Smit, G.J.M. 593 Fitsillis, P., see Kameas, A. 755 Jemai, A., see Berger Sabbatel, G. 497 Fortes, J., see Miranda, J. 625 Jezieniecki, R. and E. Rovaris, An image distance Fourman, M.P., see Mayger, E.M. 667 measure insensitive to amplitude and mean value Frances, M.D., see Mayger, E.M. 667 variations 453 Francois, J.A., see Compan, A. 637 Jokitalo, P., see Rautiola, K. 565 Freericks, M., see Knoll, A. 541 Jézwiak, L. and J.C. Kolsteren, An efficient method Frieder, O., see Van Trees, S.P. 739 for the sequential general decomposition of sequential machines 657 Ganz, A., see Chlamtac, I. 575 Gianuzzi, V., see Clematis, A. 365 Kacsuk, P., Implementing Prolog on a DAP/multi- Giavitto, J.L., see Delaplace, F. 153 transputer computer 471 Goutis, C.E., see Kyrloglou, N.A. 425 Kameas, A., P. Fitsillis and G. Pavlides, Algorithms Goutis, C.E., see Nikolaidis, S.S. 557 for inference control 755 Grabner, J., see Brenner, E. 799 Kapus-Kolar, M., Deriving protocol specifications Grosspietsch, K.E., see Buddefeld, J. 335 from service specification parameters 731 Grupe, V., see Rauscher, R. 163 Kattilakoski, M., see Honka, H. 127 Author index 875 Kaxiras, S., see Tsanakas, P. 307 Mitterbauer, R., Concept for a_ self-calibrating Kenneally, W.P., see Sorensen, H. 489 floatingpoint-converter for audio-applications 717 Kienzle, M.G., see Chlamtac, |. 575 Molenkamp. B., see Smit, G.J.M. 593 Kim, B.W., see Huang, B.Y. 765 Montenegro, R., see Ferragut, L. 61 Klein-Hessling, G., see Schafer, M. 299 Moon, S.C., see Huang, B.Y. 765 Klinke, R., see Buddefeld, J. 335 Moon, S.C., see Lim, J.T. 747 Knoll, A. and M. Freericks, An applicative real-time Moosburger, M., see Brenner, E. 799 language for DSP-programming supporting Mozos, D., see Septién, J. 185 asynchronous data-flow concepts 541 Muller, G., B. Rochat and P. Sanchez, A stable Koehl, J., see Tietz, A. 227 transactional memory for building robust object Kolsteren, J.C., see J6zwiak, L. 657 oriented programs 359 Koufopaviou, O.G., see Nikolaidis, S.S. 557 Muller-Wipperfirth, T. and H. Hellwagner, LISAS - Koyandis, A., see Kyrloglou, N.A. 425 simulation tool for regular networks of finite state Krohm, F., see Haeck, H.-G. 193 machines 651 Kuchcinski, K., see Cu, X. 835 Murphy, S.J.M., see Sorensen, H. 489 Kwok, D.P., P. Wang and C.K. Li, A combined fuzzy Musgrave, F., see Mayger, E.M. 667 and classical PID controller 701 Kyrloglou, N.A., S. Koutroubinas, A. Koyandis and Nagy, Z., see Sziray, J. 525 C.E. Goutis, A placing and routing tool Nain, T.S., see Hsieh, W.S. 723 implemented in Prolog 425 Nain, T.S., see Huang, K.C. 281 Koutroubinas, S., see Kyrloglou, N.A. 425 Nani, G., see Ancona, M. 263 Navarro, D., A. Roy, M. Robert, M. Deschacht and D. Lakshmi Narasimhan, V. and T. Downs, Fault tolerant Auvergne, TVA : a timing verifier with analytic aspects of a dynamic dataflow architecture -- temporal modelling 645 PATTSY 243 Navarro. J.J., see Fernandez, A. 825 Lazure, D., see Hemery, F. 137 Neejarvi, J., V. Fischer, S. Alenius and V. Neuvo, Lehner, F., Software life cycle management based on Knowledge-based segmentation using morphol- a phase distinction method 603 ogical filters 447 Leng, P., see Chariton, C. 93 Neuvo, V., see Neejarvi, J. 447 Li, C.K., see Kwok, D.P. 701 Nikolaidis, $.S., O.G. Koufopavlou, S. Theodoridis, Lim, J.T. and §.C. Moon, Global checkpointing and C.E. Goutis, Array processor for LS FIR scheme for heterogeneous distributed database system identification 557 systems 747 Nufiez, A., see Eshraghian, K. 75 Lin, |., see Huang, K.C. 281 Ndfez, A., see Ferragut, L. 61 Lin, K.-J., see Tu, P. 119 Lins, R.D., A shared memory architecture for parallel O'Flaherty, F.B., see Sorensen, H. 489 cyclic reference counting 53 O'Mahony, A.B., see Sorensen, H. 489 Llaberia, J.M., see Fernandez, A. 825 Oliveira, S.C., see Aude, J.S. 45 Lock, H.C.R. and A. Martin, Issues in the Otschko, G., see Brenner, E. 799 implementation of Prolog, and their optimization 505 45 Lombardi, F., see Buonanno, G. 775 Pacheco Jr, A.C., see Aude, J.S. 263 Lopes, F., see Silva, V. 343 Paci, M., see Ancona, M. 307 Lou, D.C., see Yang, C.S. 583 Papakonstantinou, G., see Tsanakas, P. Lu, C.S., see Hsieh, W.S. 723 Pataricza, A., Remarks on the use of Reed-Solomon Lu, C.S., see Huang, K.C. 281 codes in signature analysis 843 Luque, E., R. Suppi, J. Sorribes, M.A. Mayosky and Pavlides, G., see Kameas, A. 775 M.A. Senar, Simulation and visualization tools for Pawlak, A., see Wrona, W. 85 link-based parallel architectures 479 Pécheux, F., see Compan, A. 637 Peng, Z., see Cu, X. 835 MacDonald, A., see Zimmer, R. 691 Peter, J.-L., Design of a custom DRAM storage unit Manoli, Y., see Haeck, H.-G. 193 coupled to i486(tm) 179 Martin, A., see Lock, H.C.R. 505 Pissaloux, E., see Bouaziz, S. 39 Mastretti, M., see Antoniazzi, S. 315 Pongracz, J., see Erenyi, |. 807 Mayger, E.M., M.D. Francis, R.L. Haris, F. Musgrave Power, D.M.J., see Sorensen, H. 489 and M.P. Fourman, The need for a core method 667 Preece, C., see Wingate, G.A.S. 861 Mayosky, M.A., see Luque, E. 479 Mehaut, J.-F., see Hemery, F. 137 Rauscher, R. and V. Grupe, Use of mathematical Mehrez, H., see Compan, A. 637 procedures for the task of power measurement Mérigot, A., see Bouaziz, S. 39 and the corresponding VLSI-realization 163 Meslin, A.M., see Aude, J.S. 45 Rautiola, K. and P. Jokitalo, DSP-architecture design Miranda, J. and J. Fortes, A Modula-2-like systems with a Petri-net-based simulator 565 programming language and its implementation 625 Refenes, A.N., see Balou, A.T. 289 876 Author index Refenes, A.N. and C. Alippi, Histological image Suppi, R., see Luque, E. 479 understanding by error backpropagation 437 Sziray, J. and Z. Nagy, OPART: a_ hardware- Rivers, M., see Charlton, C. 93 description language for test generation 525 Robert, M., see Navarro, D. 645 Rochat, B., see Muller, G. 359 Theodoridis, S., see Nikolaidis, S.S. 557 Rodrigues, A., see Silva, V. 343 Tietz, A. and J. Koehl, A VLSI - CAD system for Roethe, M. and U. Wille, ACMOS implementation of efficient design of CMOS/390 processors 227 the ESA/390 mainframe architecture 209 Tirado, F., see Septién, J. 185 Rovaris, E., see Jezieniecki, R. 453 Tsai, S.R. and R.J. Chen, Interprocess communica- Roy, A., see Navarro, D. 645 tion with multicast support in DMINIX operating system 145 Sacha, K., Transnet: a method for transformational Tsanakas, P., G. Papakonstantinou and S. Kaxiras, A development of embedded software 617 Prolog-based design environment for the high- Sagoo, J.S. and J. Holding, A comparison of level synthesis of application-specific architectures temporal Petri net techniques in the specification Tseng, J.R., see Hsieh, W.S. and design of hard real-time systems Tu, P. and K.-J. Lin, Minimizing the maximum Sanchez, P., see Muller, G. lateness in real-time computations with extended Sarmiento, R., see Eshraghian, K. deadlines Schaefer, D.H., Massively parallel computers - past, Turski, W.M., Invisible laws and public myths of present and future programming Schafer, M. and G. Klein-Hessling, A design concept Tyrrell, A.M., see Carpenter, G.F. for verified concurrent controllers Tzeng, J.S., see Yang, C.S. Schill, A., Language and runtime support for distributed object groups Uceda, J., see Aguado, M.J. Schldgl, K., see Brenner, E. Ungerer, T., Parallelising C++-programs for Schmidt, J., see Servit, M. transputer systems Schmitt-Landsiedel, D., see Eisele, V. Schmunkamp, D., The clock, test and maintenance Van Trees, S.P. and O. Frieder, On the specification control chip of the IBM ES/9221 and implementation of X.25 using CSP and Schweinzer, H. and G. Stadibauer, A multiprocessor Occam bus system with cyclic data exchange for Valeno-Gracia, M., see Fernandez, E. the field of control and signalprocessing Vasconcelos, M.Q., see Fernandes, E.S.T. Schweinzer, H., see Steininger, A. Verschueren, A., see Hu, Y.-C. Sciuto, D., see Hadjinicolaeu, M. Vierhaus, H.T., see Hubner, U. Sciuto, D., see Buonanno, G. Seifter, P., see Brenner, E. Wagner, G., see Buddefeld, J. Senar, M.A., see Luque, E. Wallach, Y. and E. Yaprak, Parallel solution of state- Septién, J., D. Mozos, R. Hermida and F. Tirado, A estimation on an IBM ring network hardware allocator guided by cost functions Wallmiller, E., Software quality management Serrano, G.L., see Fernandez, M.A.R. Wang, P., see Kwok, D.P. Servit, M. and J. Schmidt, Strategy of one and half Watson, B.W., W.J. Withagen and M.P.J. Stevens, layer routing Compilation techniques for high level language Shen, Y.-N., see Buonanno, G. processor Silva, V., L. Cruz, F. Lopes, A. Rodrigues and L. de Weiss, R., see Brenner, E. $4, Multiprocessor based image coding 343 Wille, U., see Roethe, M. Smit, G.J.M., P.J.M. Havinga, P.G. Jansen, F. De Wingate, G.A.S. and C. Preece, Analysis of failure Boer and B. Molenkamp, On hardware for data collected from a TMR microprocessor generating routes in Kautz digraphs 593 controller Song, J., see Brenner, E. 799 Winter, G., see Ferragut, L. Sorensen, H., T.A. Delaney, W.P. Kenneally, S.J.M. Withagen, W.J., see Watson, B.W. Murphy, F.B. O'Flaherty, A.B. O'Mahony, D.M.J. Wrona, W. and A. Pawlak, VLSI integrated circuit Power, Towards a development environment for design representation in an _ object-oriented fifth generation systems 489 CAD environment Sorribes, J., see Luque, E. 479 Wu, S.Y., see Yang, C.S. 589 Stadibauer, G., see Schweinzer, H. 709 Steger, Ch., see Brenner, E. 799 Yang, C.S., W.S. Hsieh, D.C. Lou and J.S. Tzeng, S Steininger, A. and H, Schweinzer, Towards an regular interconnection network 583 optimal combination of error detection Yang, C.S., S.Y. Wu and K.C. Huang, A reconfigur mechanisms 253 able modular fault tolerant generalized Boolean n- Stevens, M.P.J., see Bendens, L.P.M. 323 cube network 589 Stevens, M.P.J., see Hu, Y.-C. 101 Yang, M.S., see Hsieh, W.S. 723 Stevens, M.P.J., see Watson, B.W. 29 Yang, M.S., see Huang, K.C. 281 Author index 877 Yaprak, E., see Wallach, Y. 817 Zimmer, R., A. MacDonald and R. Holte, CAD for verified hardware design via category theory 691 Zara, G., see Hadjinicolaeu, M. 675 Microprocessing and Microprogramming 32 (1991) 879-882 879 North-Holland SUBJECT INDEX abstraction mechanism 271 data communication 575 access method 765 data consistency 215 analytic temporal modelling 645 data environment 263 application development 609 data path synthesis 193 application language 541 data persistence 263 application-oriented VLSI 807 dataflow computing 243 application-specific architecture 307 deadlock elimination 243 Architectural Design Support Environment (ADSE) 315 design environment 307 architectural evaluation 69 design trajectory 531 architecture synthesis 683 design verification 667 array processor 557 development environment 489 artificial neural network 335 digital signal processing 541 asynchronous dataflow 541 distance measure 453 automatic test pattern generation 835 distributed architecture 401 distributed environment 401 backpropagation 437 distributed object cooperation 271 batching arbiter 243 distributed object group 271 behavioural specification 517 distributed runtime protocol 271 binary division 13 distributed system 271, 575 Distributed Array Processor (DAP) ? C++ 359, 463 division 13 C-processor 29 division instruction 13 CAD 227 DMINIX operating system 145 CAD system 93 DSP-architecture 565 category theory 691 checkpointing scheme 747 osnedtnd cose 215 CiSC-architecture 209 clock optimization 227 oe vena wo Clock, Test and Maintenance (CTM) control chip 221 ind reneanraeiti ee Ce) CMOS combinational circuit 775 sebeilisoggenyinerc idcee mmegconeg pest ESPRIT Ii PATRICIA project 675 CMOS implementation 209 expert system CAD tool 675 CMOS waferscale integration 335 ad : extended deadline 119 communication mechanism 39 communication protocol 281 compilation technique 29 failure analysis 861 complexity evaluation 683 fault coverage 791 compound queries algorithm 755 fault detection 775, 783 computer architecture 13 fault diagnosis 799 computer arithmetic 13 fault elimination 853 computer vision 807 fault list handling 853 concurrent ADA programs 365 fault tolerance 171, 237, 243, 253, 365, 373 concurrent system 373 fault-tolerant architecture 589 control 709 Fault Tolerant Multiprocessor (FTM) 359 controller architecture 299 feature extraction 807 Coordinate Rotation Digital Computer (CORDIC) 349 fifth generation system 489 cost function 185 Finite State Machine (FSM) 281, 651 CSP 739 floating point adder generator 637 custom storage unit 179 floating point converter 717 CXgen function library 637 formal method 667 cyclic data exchange 709 fuzzy controller 701 880 Subject index GaAs integrated circuit 75 object-oriented 263 generalized Boolean n-cube network 589 object-oriented concurrentlanguage 137 object-oriented interface 463 hard real-time system 111 object-oriented modelling 93 hardware allocation 199 object-oriented programming 85 hardware allocator 185 object-oriented system analysis 101 HDL 525 Occam 739 Helios operating system 137 Occam programming 393 Heterogeneous Distributed Database System open system 401 (HDBMS) 747 operation scheduling 199 Hidden Markov Models (HMM) 549 optimization 69, 75 High Performance Parallel Interface (HIPPI) 575 order recursive algorithm 557 high-level language processor 29 high-performance digital system 315 parallel architecture 171 HLD language 413 parallel computer 237, 289 host environment 127 parallel cyclic reference counting 53 parallel image sensing 335 IBM ring network 817 parallel processing 45 image coding 343 parallel processor simulation 479 image data reduction 453 parallel program 479 image understanding 437 parallel programming 463 incremental design 227 parallel solution 817 industrial quality control 807 parallel transmission lines analysis 61 inference control 755 performance evaluation 825 integrated software environment 393 performance visualization 479 Intel i486(tm) microprocessor 179 Petri net 799 interconnect capacitance 61 Petri-net based simulator 565 interconnection network 593 Petri-net technique 111 interprocess communication 145 phase distinction 603 interval temporal logic 517 power measurement 163 problem domain entities 101 Kautz graph 593 process migration 153 programming environment 401 language extension 271 programming myths 3 large distributed system 583 Prolog 307, 425, 471, 497 linear algebra problem 825 Prolog implementation 505 load-balancing mechanism 153 Proportional-integral-Derivative (PID) controller 701 protocol specification 731 massively parallel computer 7, 39 protocol validation 723 Massively Parallel Mixed Architecture (MAPMAS) 471 Protocol Validation Development (PVD) 281 mathematical procedure 163 message passing 137 real-time computation 119 micro-instruction 23 real-time embedded software 127 micro-instruction algorithm 23 real-time expert system 799 microcontroller instruction set 193 real-time system 861 microprocessor system reliability 861 real-time video 343 MIMD 7, 39, 45, 171 reconvergent fanout analysis 835 MINIX 145 Reed-Solomon codes 843 Modula-2 625 regular combinatoric structures 69 modular manufacturing system 799 regular interconnection network 583 morphological filter 447 ring notation 75 MOS transistor network 783 RISC processor 497 MULPLIX operating system 45 rollover mechanism 243 multi-SIMD 39 routing 417, 425 multicast support 145 routing algorithm 593 multidimensional complex object 765 routing hardware 593 multilayered dielectric media 61 routing strategy 153 MULTIPLUS 45 multiprocessor bus system 709 segmentation 447 multiprogramming 137 sequential general decomposition 657 sequential machine 531, 657 networking 575 service specification 731 Subject index 881 shared memory 45, 53 testability measure 835 signal processing 709, 807 texture analysis 807 signature analysis 843 3D hardware package 171 SIMD 7 timing driven design 227 SIMM 179 timing verifier 645 simulated annealing 23 tools integration 401 simulation environment 479 transformational development 617 simulation tool 651 transputer 463 singular value decomposition 453 transputer system 825 SMALLTALK 85 software lifecycle management 603 user interface generator 401 software quality management 609 spatial database 765 vector generation 853 speech recognition 549 verified concurrent controller 299 stable state exploration 723 verified hardware design 691 Stable Transaction Memory (STM) 359 VHDL 85, 323, 593 state estimation 817 Virtual Object Oriented Machine (VOOM) 289 system identification 557 visual language 383 system specification 383 visualization tool 479 systems programming language 625 VLSI 101, 227 VLSI design environment 85 temporal logic 111 VLSI-realization 163 temporary fault 861 test generation 525, 791 X.25 implementation 739 Test Access Bus (TAB) 221 X.25 specification 739 testability analysis 675