Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems

234 Pages·2012·4.874 MB·English

by  Benny Akesson, Kees Goossens (auth.)

Embedded Systems
SeriesEditors
NikilD.Dutt,DepartmentofComputerScience,ZotCode3435,DonaldBren
SchoolofInformationandComputerSciences,UniversityofCalifornia,Irvine,
CA92697-3435,USA
PeterMarwedel,TUDortmund,Informatik12,Otto-Hahn-Str.16,44227
Dortmund,Germany
GrantMartin,TensilicaInc.,3255-6ScottBlvd.,SantaClara,CA95054,USA
Forfurthervolumes:
http://www.springer.com/series/8563
Benny Akesson Kees Goossens
•
Memory Controllers
for Real-Time Embedded
Systems
Predictable and Composable Real-Time
Systems
123
BennyAkesson KeesGoossens
FacultyofElectricalEngineering FacultyofElectricalEngineering
EindhovenUniversityofTechnology EindhovenUniversityofTechnology
Potentiaal/PT9.11,DenDolech2 Potentiaal/PT9.34,DenDolech2
5600MBEindhoven 5600MBEindhoven
Netherlands Netherlands
[email protected] [email protected]
ISBN978-1-4419-8206-3 e-ISBN978-1-4419-8207-0
DOI10.1007/978-1-4419-8207-0
SpringerNewYorkDordrechtHeidelbergLondon
LibraryofCongressControlNumber:2011934803
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Preface
The authors of this book first met in the context of a master project in Philips
Research in Eindhoven,the Netherlands,back in the summer of 2004.One was a
studentinComputerScienceandEngineeringfromLundUniversityofTechnology
in Sweden, and the other a principal research scientist, leading the team of
researchersdesigningapredictablenetwork-on-chipcalledÆthereal.Theworkon
thenetwork-on-chiphadbeengoingonforseveralyears,andtheteamhadrealized
thatpredictablesystem-levelguaranteesalsorequiredapredictablesolutionforthe
memorysystem,whichwasthetopicofthemasterproject.
Inspiration for the memory controller designed in this project was found in
twodifferentgroupswithinPhilips.OnegroupmadestaticallyscheduledSDRAM
controllersforhigh-performancevideopipelineswithfirmreal-timerequirements,
which inspired the idea of precomputed memory patterns. The other group made
dynamically scheduled memory controllers for digital TV and set-top boxes, re-
quiringdynamicschedulingtoreducelatenciesoflatency-sensitivememoryclients.
Thememorycontrollerproposedinthisbookisahybriddesignthatcombinesthe
approachesofthesegroupsbydynamicallyschedulingstaticallycomputedmemory
patterns.Fromthese twogroups,theauthorswouldparticularlyliketo thankFrits
SteenhofandAdSiereveldfortheinspirationandcreativediscussions.
Attheendofthe9monthmasterproject,itwasclearthatonlythesurfaceofa
largeresearchtopichadbeenscratchedandthatmuchinterestingworkremainedto
be done. An opportunityto continue the work in the Electronic Systems group at
EindhovenUniversityofTechnologypresenteditselfthroughaPhilips-fundedPhD
positioninthePreMaDoNaproject.Thebulkoftheresearchpresentedinthisbook
wascarriedoutinthescopeofthisprojectduringthefollowing4yearsandresulted
in a thesis, several publications, and both a simulation model and a hardware
implementationofthememorycontrollerintegratedinadesignflow.Thiswouldnot
have been possible without the contributionsfrom severalmaster students. Thank
youMarkusRinghofer,EelkeStrooisma,GetachewTeshome,WillistonHayes,and
Winston Siauw for your hard work and for all the good times. The authors also
v
vi Preface
expresstheirgratitudetoProf.LambertSpaanenburgandProf.JefvanMeerbergen
forbeingthekeyenablersofthemasterprojectandthePhDproject,respectively.
DuringthePhDproject,partsofPhilipsResearchturnedintoNXPSemiconduc-
tors, andthe researchon the Ætherealnetwork-on-chipfinished.The fruitsof this
research were combined with processor tiles featuring Silicon Hive VLIW cores
and MicroBlaze cores, resulting in the CoMPSoC platform and design flow. This
effort demonstrated that it was possible to design a predictable and composable
platform capable of concurrently executing a mix of real-time and non-real-time
applications.Sincethen,thisplatformhasbeenextensivelyusedbothasaresearch
vehicleandforembeddedsystemeducationatEindhovenUniversityofTechnology,
DelftUniversityofTechnology,andNXPSemiconductors.
For every door you close in research, another one opens. Both authors of this
book are currently employed at Eindhoven University of Technology extending
the workonthe CoMPSoCplatformand thepredictableandcomposablememory
controller.TheauthorsexpresstheirgratitudetoallthemembersoftheCoMPSoC
team, and in particular to those contributing to the memory controller research.
ThankyouKarthikChandrasekar,FirewSiyoum,AnandKhot,SvenGoossens,Tim
Kouters,andManilDevGomony,forcontinuingtopushtheboundariesofreal-time
memorycontrollers.
Hard and passionate work takes its toll and sacrifices evenings and weekends
when required. The authors are grateful for the support from family and friends,
in particular for the friendship and help from Andreas Hansson. Finally, Benny
acknowledges the support of his wife María Eugenia Martelli, whose love and
understandingmadethisjourneyeasierandmoreenjoyable.
Eindhoven,theNetherlands BennyAkessonandKeesGoossens
Intended Audience
This book is generally intended for readers interested in Systems-on-Chips with
real-time applications. It targets senior architects and engineers, as well as aca-
demics (both teachers and students), looking for a perspective on the design and
useofmemorycontrollersinthesesystems.Itisespeciallywell-suitedforreaders
lookingto use SDRAM memories in systems with hard or firm real-time require-
ments.Thebookprovidesenoughbackgroundonmemoriesandmemorycontrollers
tobeself-containedandprovidesextensivebackgroundreferencesfortheinterested
reader. There is a strong focus on real-time concepts, such as predictability and
composability, and only a brief discussion about memory controller architectures
forhigh-performancecomputing.
The reader learns step-by-step how to go from an unpredictable SDRAM
memory offering highly variable bandwidth and latency to a predictable and
composablesharedmemoryprovidingguaranteedbandwidthandlatencytoisolated
applications.Thisjourneycoversconceptsformakingmemoriesandarbitersbehave
in a predictable and composable manner, as well as architecture descriptions of
hardwareblocksthatimplementtheconcepts.
The book will appeal to readers with different levels of prior knowledge and
differentlearninggoals:
Novice/student & teachers: learns/teaches about system verification trends and
challenges, the general architecture of SDRAM and memory controllers, and the
problemofusingtheseinSystems-on-Chipswithreal-timeapplications.
Practitioner: learns about concrete concepts, architectures, and implementations
forpredictableandcomposablememorycontrollers.
Expert: learnsaboutcompletedesignphilosophyandconceptsforpredictableand
composable memory controllers that are directly applicable to different system
approaches,suchastime-triggeredarchitectures,precision-timedarchitectures,and
differentplatforms,suchasMERASAandCoMPSoC.
vii
Contents
1 Introduction.................................................................. 1
1.1 TrendsinEmbeddedSystemDesign.................................. 2
1.1.1 Applications ................................................... 2
1.1.2 Platform-BasedDesign........................................ 4
1.1.3 PlatformArchitecture ......................................... 7
1.1.4 Mapping........................................................ 10
1.1.5 Verification..................................................... 12
1.1.6 SDRAMandReal-TimeRequirements....................... 13
1.2 ProblemStatement..................................................... 15
1.3 Requirements........................................................... 16
1.3.1 Predictability................................................... 16
1.3.2 Abstraction..................................................... 18
1.3.3 Composability ................................................. 19
1.3.4 Automation .................................................... 21
1.4 SystemContext ........................................................ 21
1.5 Contributions........................................................... 24
1.6 Outline.................................................................. 25
1.7 Summary............................................................... 26
2 ProposedSolution........................................................... 29
2.1 Predictability........................................................... 29
2.1.1 OverviewofApproach........................................ 29
2.1.2 PredictableSDRAMBack-End............................... 30
2.1.3 PredictableArbitration........................................ 34
2.2 Abstraction............................................................. 36
2.3 Composability.......................................................... 38
2.4 Automation............................................................. 41
2.5 Summary............................................................... 42
3 SDRAMMemoriesandControllers....................................... 45
3.1 IntroductiontoSDRAM............................................... 45
ix
x Contents
3.1.1 SDRAMArchitecture......................................... 46
3.1.2 TheSDRAMProtocol......................................... 47
3.1.3 TimingConstraints ............................................ 48
3.2 FormalModel.......................................................... 49
3.3 MemoryEfficiency .................................................... 50
3.3.1 RefreshEfficiency............................................. 51
3.3.2 Read/WriteEfficiency......................................... 51
3.3.3 BankEfficiency................................................ 52
3.3.4 CommandEfficiency.......................................... 52
3.3.5 DataEfficiency ................................................ 52
3.3.6 GrossandNetEfficiencies.................................... 53
3.3.7 MemoryEfficiencyTrend..................................... 54
3.4 MemoryControllers................................................... 54
3.4.1 BusandArbiter................................................ 55
3.4.2 CommandGenerator .......................................... 56
3.4.3 MemoryMap .................................................. 57
3.5 Summary............................................................... 60
4 PredictableSDRAMBack-End............................................ 63
4.1 OverviewofPredictableSDRAMController ........................ 63
4.1.1 Arbitration ..................................................... 64
4.1.2 CommandGenerator .......................................... 64
4.1.3 MemoryMap .................................................. 65
4.2 MemoryPatterns....................................................... 65
4.2.1 SchedulingRules.............................................. 66
4.2.2 PatternDescriptions........................................... 66
4.2.3 PatternSetDominance........................................ 68
4.3 MemoryEfficiencyBound ............................................ 70
4.3.1 RefreshEfficiency............................................. 70
4.3.2 Read/WriteEfficiency......................................... 72
4.3.3 BankandCommandEfficiency............................... 72
4.3.4 DataEfficiency ................................................ 73
4.4 LatencyBound......................................................... 75
4.5 MemoryPatternGeneration........................................... 77
4.5.1 DesignDecisions.............................................. 78
4.5.2 AccessPatternTermination................................... 81
4.5.3 BranchandBound............................................. 82
4.5.4 As-Soon-As-PossibleScheduling............................. 85
4.5.5 BankScheduling............................................... 87
4.5.6 ComputingAuxiliaryPatterns ................................ 88
4.6 ArchitectureandSynthesis............................................ 89
4.7 ExperimentalResults.................................................. 90
4.7.1 ExperimentalSetup............................................ 91
4.7.2 AlgorithmEvaluation ......................................... 91
4.7.3 BoundingNetBandwidth..................................... 99
Contents xi
4.7.4 TightnessofNetBandwidthBound .......................... 100
4.8 Summary............................................................... 101
5 ResourceArbitration ....................................................... 105
5.1 ArbiterRequirements.................................................. 106
5.2 FormalModel.......................................................... 106
5.2.1 RequestedServiceModel..................................... 106
5.2.2 ProvidedServiceModel....................................... 108
5.3 Latency-RateServers.................................................. 112
5.4 Time-DivisionMultiplexing........................................... 114
5.4.1 Overview....................................................... 115
5.4.2 Analysis........................................................ 116
5.5 Frame-BasedStatic-PriorityArbitration.............................. 119
5.5.1 Overview....................................................... 119
5.5.2 Analysis........................................................ 119
5.6 Credit-ControlledStatic-PriorityArbitration......................... 121
5.6.1 Overview....................................................... 121
5.6.2 ActivePeriodRateRegulation................................ 122
5.6.3 Analysis........................................................ 125
5.7 ExperimentalResults.................................................. 126
5.7.1 ExperimentalSetup............................................ 127
5.7.2 EvaluationofServiceGuarantee.............................. 127
5.7.3 LatencyDistributions.......................................... 129
5.7.4 TightnessofServiceLatencyBound ......................... 135
5.7.5 AllocationProperties.......................................... 138
5.8 Summary............................................................... 141
6 ComposableResourceFront-End ......................................... 143
6.1 OverviewofApproach ................................................ 144
6.2 FormalModel.......................................................... 146
6.3 Architecture............................................................ 149
6.3.1 ArchitectureOverview ........................................ 149
6.3.2 Atomizer....................................................... 150
6.3.3 DelayBlock.................................................... 150
6.3.4 DataBus ....................................................... 154
6.3.5 SynthesisResults.............................................. 155
6.4 Experiments............................................................ 158
6.4.1 SRAMExperiments........................................... 158
6.4.2 SDRAMExperiments......................................... 165
6.5 Summary............................................................... 168
7 Configuration................................................................ 171
7.1 FormalModel.......................................................... 171
7.2 MemoryPatternGeneration........................................... 173
7.3 NormalizationofRequirements....................................... 175
7.4 ArbiterConfiguration.................................................. 177
xii Contents
7.4.1 BandwidthAllocation......................................... 178
7.4.2 PriorityAssignment........................................... 180
7.5 DenormalizationofAllocation........................................ 181
7.6 RequirementVerification.............................................. 182
7.7 ExperimentalResults.................................................. 184
7.8 Summary............................................................... 186
8 RelatedWork ................................................................ 187
8.1 ResourceArbitration................................................... 187
8.2 SDRAMControllers................................................... 189
8.3 ComposableService................................................... 192
9 ConclusionsandFutureWork............................................. 195
9.1 Conclusions............................................................ 195
9.1.1 Predictability................................................... 196
9.1.2 Abstraction..................................................... 196
9.1.3 Composability ................................................. 197
9.1.4 Automation .................................................... 197
9.2 FutureWork............................................................ 198
9.2.1 ReducingPowerConsumption................................ 198
9.2.2 Opportunitieswith3DIntegration............................ 198
9.2.3 ImprovedArbiterConfiguration.............................. 199
9.2.4 Reconfiguration................................................ 200
9.2.5 Data-FlowModelofMemoryController..................... 200
A SystemXMLSpecification ................................................. 203
A.1 ArchitectureSpecification............................................. 203
A.2 Use-CaseSpecification................................................ 205
B Glossary ...................................................................... 207
B.1 ListofAbbreviations.................................................. 207
B.2 ListofSymbols........................................................ 208
References......................................................................... 211
Index............................................................................... 219