MAX11900 16-Bit, 1Msps, Low-Power, Fully Differential SAR ADC

29 Pages·2015·0.91 MB·English

MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
General Description Benefits and Features
The MAX11900 is a 16-bit, 1Msps, single-channel, fully ● High DC/AC Accuracy Improves Measurement
differential SAR ADC with internal reference buffers. The Quality
MAX11900 provides excellent static and dynamic perfor- • 16-Bit Resolution with No Missing Codes
mance with best-in-class power consumption that directly
• 1Msps Throughput Rates Without Pipeline Delay/
scales with throughput. The device has a unipolar differ-
Latency
ential ±VREF input range. Supplies include a 3.3V supply • 95.6dB SNR and -115dB THD at 10kHz
for the reference buffers, a 1.8V analog supply, a 1.8V
digital supply, and a 1.5V to 3.6V digital interface supply. • 0.4 LSBRMS Transition Noise
• ±0.25 LSB DNL (max) and ±0.5 LSB INL (max)
This ADC achieves 95.6dB SNR and -115dB THD, guar-
antees 16-bit resolution with no-missing codes and 0.5 ● Highly Integrated ADC Saves Cost and Space
LSB INL (max). • Internal Reference Buffer
The MAX11900 communicates data using a SPI- ● Wide Supply Range and Low Power Simplify Power-
compatible serial interface. The MAX11900 is offered in a Supply Design
20-pin, 4mm x 4mm, TQFN package and is specified over • 1.8V Analog Supply
the -40°C to +85°C operating temperature range. • 1.5V to 3.6V Digital Supply
• 6.7mW Power Consumption at 1Msps
Applications
• 6.7µW Power Consumption at 1ksps
● Test and Measurement
• 1μA in Shutdown Mode
● Automatic Test Equipment
● Multi-Industry Standard Serial Interface and Small
● Medical Instrumentation
Package Reduces Size
● Process Control and Industrial Automation • SPI/QSPI™/MICROWIRE®/DSP-Compatible
● Data Acquisition Systems Serial Interface
• 4mm x 4mm 20-Pin TQFN Package
● Telecommunications
● Battery-Powered Equipment
Ordering Information and Selector Guide appears at end of
data sheet. QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Application Diagram
Semiconductor Corporation.
1.5 TO
3.3V 3.6V 1.8V 1.8V 3.6V
16-Bit to 20-Bit SAR ADC Family
10Ω REFVDDAVDD DVDDOVDD
0 TO 3.3V AIN+REFIN DIN 16-BIT 18-BIT 20-BIT
C20nGF MAX11900 DSOCULKT 4SIN-PWTIEIRREFACE 1.6Msps MAX11901 MAX11903 MAX11905
10Ω AIN- CNVST 1Msps MAX11900 MAX11902 MAX11904
REF A D
3.3V TO 0 REF REFGND GND GND
10µF
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX11900.related.
19-7510; Rev 0; 2/15
MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
TABLE OF CONTENTS
General Description............................................................................ 1
Applications .................................................................................. 1
Benefits and Features .......................................................................... 1
Application Diagram............................................................................ 1
16-Bit to 20-Bit SAR ADC Family ................................................................. 1
Absolute Maximum Ratings...................................................................... 4
Package Thermal Characteristics ................................................................. 4
Electrical Characteristics ........................................................................ 4
Typical Operating Characteristics ................................................................. 8
Pin Configuration ............................................................................. 12
Pin Description............................................................................... 12
Functional Diagram ........................................................................... 13
Detailed Description........................................................................... 14
Analog Inputs ..............................................................................14
Input Settling...............................................................................16
Input Filtering ..............................................................................16
Voltage Reference Configurations ..............................................................17
Transfer Function ...........................................................................17
Digital Interface .............................................................................. 19
SPI Timing Diagram .........................................................................20
Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Register Read..............................................................................22
Register Map ................................................................................ 23
Mode Register..............................................................................23
Conversion Result Register ...................................................................24
Chip ID Register ............................................................................24
Typical Application Circuit ...................................................................... 24
Single-Ended Unipolar Input to Differential Unipolar Output ..........................................24
Single-Ended Bipolar Input to Differential Unipolar Output ...........................................24
Layout, Grounding, and Bypassing ............................................................... 24
Definitions................................................................................... 27
Integral Nonlinearity.......................................................................27
Differential Nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Offset Error .............................................................................27
Gain Error...............................................................................27
Signal-to-Noise Ratio......................................................................27
Signal-to-Noise Plus Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
TABLE OF CONTENTS (continued)
Effective Number of Bits ...................................................................27
Total Harmonic Distortion ..................................................................27
Spurious-Free Dynamic Range..............................................................27
Aperture Delay...........................................................................27
Aperture Jitter ...........................................................................27
Full-Power Bandwidth .....................................................................27
Selector Guide............................................................................... 28
Ordering Information .......................................................................... 28
Chip Information.............................................................................. 28
Package Information .......................................................................... 28
Revision History.............................................................................. 29
LIST OF FIGURES
Figure 1. Signal Ranges........................................................................ 14
Figure 2. Simplified Model of Input Sampling Circuit.................................................. 15
Figure 3. Conversion Frame, SAR Conversion, Track and Read Operation................................ 15
Figure 4. Ideal Transfer Characteristic ............................................................ 18
Figure 5. Read During Track Phase............................................................... 19
Figure 6. Read During SAR Conversion Phase...................................................... 19
Figure 7. Split Read Mode ...................................................................... 20
Figure 8. SPI Interface Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. DIN Timing for Register Write Operations .................................................. 21
Figure 10. Timing Diagram for Data Out Reading After Conversion...................................... 21
Figure 11. Mode Register Write .................................................................. 22
Figure 12. Register Read....................................................................... 22
Figure 13. Unipolar Single-Ended Input............................................................ 25
Figure 14. Bipolar Single-Ended Input............................................................. 25
Figure 15. Top-Layer Sample Layout.............................................................. 26
LIST OF TABLES
Table 1. ADC Driver Amplifier Recommendation..................................................... 16
Table 2. Voltage Reference Configurations......................................................... 17
Table 3. MAX11900 External Reference Recommendations............................................ 17
Table 4. Transfer Characteristic.................................................................. 18
Table 5. DOUT Driver Strength .................................................................. 23
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Absolute Maximum Ratings
REFVDD, REF, REFIN, OVDD to GND ..................-0.3V to +4V Continuous Power Dissipation (TA = +70°C)
AVDD, DVDD to GND .............................................-0.3V to +2V TQFN (derate 30.30mW/°C above +70°C).............2424.2mW
DGND to AGND, REFGND ..................................-0.3V to +0.3V Operating Temperature Range ...........................-40°C to +85°C
AIN+, AIN- to GND ......-0.3V to the lower of (VREF + 0.3V) and Junction Temperature ......................................................+150°C
+4V or ±130mA Storage Temperature Range ............................-65°C to +150°C
SCLK, DIN, DOUT, CNVST, to GND ...........-0.3V to the lower of Lead Temperature (soldering, 10s) .................................+300°C
(VOVDD + 0.3V) and +4V Soldering Temperature (reflow) .......................................+260°C
Maximum Current into Any Pin...........................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θJA).... ......33°C/W
Junction-to-Case Thermal Resistance (θJC) ....... ........ 2°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Input Voltage Range (Note 3) (AIN+) - (AIN-) -VREF +VREF V
Absolute Input Voltage Range AIN+, AIN- relative to AGND -0.1 VREF + V
0.1
Common-Mode Input Range [(AIN+) + (AIN-)]/2 VR0E.F1/2 - VREF/2 V+R E0F.1/2 V
Input Leakage Current Acquisition phase -1 0.001 +1 µA
Input Capacitance 32 pF
STATIC PERFORMANCE (Note 4)
Resolution N 16 Bits
Resolution LSB VREF = 3.3V 100.7 µV
No Missing Codes 16 Bits
Offset Error (Note 4) -1 ±0.1 +1 LSB
Offset Temperature Coefficient ±0.001 LSB/°C
Gain Error Referred to REFIN reference input -12 ±2 +12 LSB
Gain Error Temperature
Referred to REFIN reference input ±0.02 LSB/°C
Coefficient (Note 5)
Gain Error Referred to REF pins -3 ±1 +3 LSB
Gain Error Temperature
Referred to REF pins ±0.01 LSB/°C
Coefficient (Note 5)
Integral Nonlinearity INL -0.5 ±0.1 +0.5 LSB
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Electrical Characteristics (continued)
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Differential Nonlinearity
DNL -0.25 ±0.1 +0.25 LSB
(Note 6)
Analog Input CMR CMR DC 1 LSB/V
Power-Supply Rejection
PSR PSR vs. AVDD 0.2 LSB/V
(Note 7)
Power-Supply Rejection
PSR PSR vs. REFVDD 0.3 LSB/V
(Note 7)
Transition Noise 0.4 LSBRMS
EXTERNAL REFERENCE
REF Voltage Input Range VREF 2.5 3.3 3.6 V
Load Current IREF 1Msps, VREF = 3.3V 600 µA
REF Input Capacitance 1 nF
REFERENCE BUFFER
REFIN Input Voltage Range VREFIN VREF < (VREFVDD - 200mV) 2.5 3 VR2E0F0VmDVD - V
REFIN Input Current IREFIN 1 nA
Turn-On Settling Time CEXT = 10µF on REF pin, 20 ms
CREFIN = 0.1µF on REFIN pin
External Compensation
Capacitor CEXT REF pins 4.7 10 µF
DYNAMIC PERFORMANCE (Note 8)
Dynamic Range Internal RefBuffer, -60dBFS input 95.6 dB
Signal-to-Noise Ratio SNR Internal RefBuffer, fIN = 10kHz 95 95.6 dB
Signal-to-Noise Plus Distortion SINAD Internal RefBuffer, fIN = 10kHz, 95 95.6 dB
-0.1dBFs
Spurious-Free Dynamic Range SFDR Internal RefBuffer, fIN = 10kHz 117 dB
Total Harmonic Distortion THD Internal RefBuffer, fIN = 10kHz -115 dB
Total Harmonic Distortion THD Internal RefBuffer, fIN = 100kHz -110 dB
Total Harmonic Distortion THD Internal RefBuffer, fIN = 250kHz -100 dB
SAMPLING DYNAMICS
Throughput 0 1.0 Msps
-3dB point (targeting 20MHz) 20
Full-Power Bandwidth MHz
-0.1dB point 3
Acquisition Time tACQ 150 ns
Time delay from CNVST rising edge
Aperture Delay to time at which sample is taken for 1 ns
conversion
Aperture Jitter 3 psRMS
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Electrical Characteristics (continued)
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Analog Supply Voltage AVDD 1.7 1.8 1.9 V
Digital Supply Voltage DVDD 1.7 1.8 1.9 V
Reference Buffer Supply
REFVDD 2.7 3.3 3.6 V
Voltage
Interface Supply Voltage OVDD 1.5 3.6 V
Analog Supply Current IAVDD VAVDD = 1.8V 1.75 2.3 mA
Digital Supply Current IDVDD VDVDD = 1.8V 1.5 1.9 mA
RCeufrererenntce Buffer Supply IREFVDD VenRaEbFlVedDD = 3.6V, internal buffers 3.3 3.55 mA
RCeufrererenntce Buffer Supply IREFVDD VpoRwEeFrVeDdD d =o w3n.6V, internal buffers 0.2 mA
Interface Supply Current VOVDD = 1.5V 0.27
(Note 9) IOVDD VOVDD = 3.6V 1 mA
Shutdown Current For AVDD, DVDD, REFVDD 1 µA
Shutdown Current For DVDD 1 µA
VAVDD = 1.8V, VDVDD = 1.8V,
Power Dissipation VREFVDD = 3.3V, internal reference 6.7 8.4 mW
buffers disabled
DIGITAL INPUTS (DIN, SCLK, CNVST)
0.7 x
Input Voltage High VIH VOVDD = 1.5V to 3.6V VOVDD V
0.3 x
Input Voltage Low VIL VOVDD = 1.5V to 3.6V VOVDD V
Input Capacitance CIN 10 pF
Input Current IIN VIN = 0V or VOVDD 1 µA
DIGITAL OUTPUTS (DOUT)
Output Voltage High VOH ISOURCE = 2mA VO0V.D4D - V
Output Voltage Low VOL ISINK = 2mA 0.4 V
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Electrical Characteristics (continued)
(fSAMPLE = 1Msps, VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.5V to 3.6V, VREFVDD = 3.6V, VREF = 3.3V, Internal Ref Buffers On,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING
DIN to SCLK Rising Edge
Setup t1 4 ns
DIN to SCLK Rising Edge Hold t2 1 ns
DOUT End-Of-Conversion
Low Time t3 15 ns
DOUT to SCLK Rising
Edge Hold t4 2.5 ns
DOUT to SCLK Rising
Edge Setup t5 100MHz SCLK 1.5 ns
SCLK High t6 4.5 ns
SCLK Period t7 10 ns
SCLK Low t8 4.5 ns
CNVST Rising Edge To SCLK
Rising Edge t9 0 ns
SCLK Rising Edge to CNVST
Rising Edge t10 25 ns
CNVST High t11 25 ns
CNVST High to EOC t12 850 ns
Conversion Period t13 1000 ns
Note 2: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and device characterization.
Note 3: See the Analog Inputs section.
Note 4: See the Definitions section at the end of the data sheet.
Note 5: See the Definitions section at the end of the data sheet. Error contribution from the external reference not included.
Note 6: Parameter is guaranteed by design.
Note 7: Defined as the change in positive full-scale code transition caused by a ±5% variation in the supply voltage.
Note 8: Sine wave input, fIN = 10kHz, AIN = -0.5dB below full scale.
Note 9: CLOAD = 10pF on DOUT. fCONV = 1Msps. All data is read out.
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Typical Operating Characteristics
(VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.8V, VREFVDD = 3.6V, fSAMPLE = 1Msps, VREF = 3.3V, Internal Ref Buffer On, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
toc1
INL vs. TEMPERATURE DNL vs. TEMPERATURE
0.5 toc3 0.5 toc4
MAX INL (LSB) MAX DNL (LSB)
0.4 0.4
MIN INL (LSB) MIN DNL (LSB)
0.3 0.3
0.2 0.2
INL (LSB)-000...011 DNL (LSB)-000...011
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (oC) TEMPERATURE (oC)
INL vs. AVDD SUPPLY VOLTAGE DNL vs. AVDD SUPPLY VOLTAGE
0.5 toc5 0.5 toc6
0.4 MMAINX I NINLL ( (LLSSBB)) VVRREEFFV=D D3=.3 3V.6V 0.4 MMAINX D DNNLL ( (LLSSBB)) VVRREEFFV=D D3=.3 3V.6V
0.3 0.3
0.2 0.2
INL (LSB)-000...011 DNL (LSB) -000...011
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
1.70 1.75 1.80 1.85 1.90 1.70 1.75 1.80 1.85 1.90
VAVDD(V) VAVDD(V)
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.8V, VREFVDD = 3.6V, fSAMPLE = 1Msps, VREF = 3.3V, Internal Ref Buffer On, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
INL vs. REFVDD SUPPLY VOLTAGE DNL vs. REFVDD SUPPLY VOLTAGE
0.5 toc7 0.5 toc8
0.4 MAX INL (LSB) VAVDD= 1.8V 0.4 MAX DNL (LSB) VAVDD= 1.8V
MIN INL (LSB) VREF= 2.5V MIN DNL (LSB) VREF= 2.5V
0.3 0.3
0.2 0.2
INL (LSB)-000...011 DNL (LSB)-000...011
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VREFVDD(V) VREFVDD(V)
OFFSET AND GAIN ERROR vs. TEMPERATURE OFFSET AND GAIN ERROR vs. AVDD SUPPLY VOLTAGE
2.0 toc9 2.0 toc10
1.5 OGFAFINE SETR REORRR O(LRS (BL)SB) VVRREEFFV=DD3=.3 V3.6V 1.5 OGfafsine tE Errroror r( L(SLSBB)) VRVERFEVFDD= =3 .33.V6V
1.0 1.0
ERROR (LSB)-000...055 ERROR (LSB) -000...055
-1.0 -1.0
-1.5 -1.5
-2.0 -2.0
-40 -25 -10 5 20 35 50 65 80 95 110 125 1.7 1.75 1.8 1.85 1.9
TEMPERATURE (°C) VAVDD (V)
OFFSET AND GAIN ERROR vs. REFVDD VOLTAGE OUTPUT NOISE HISTOGRAM
2.0 toc11 320000 toc12
Offset Error (LSB) STDEV = 0.18 LSB
1.5 VREF= 2.5V 280000
Gain Error (LSB) VAVDD= 1.8V
1.0 S 240000
OFFSET ERROR (LSB) --1000....0505 MBER OF OCCURRENCE11282600000000000000000
U
N
-1.5 40000
-2.0 0
2.7 2.8 2.9 3 3.V1REFVDD 3(V.2) 3.3 3.4 3.5 3.6 32772.0 32772.5 32773.0 32773.5 32774.0 32774.5 32775.0 32775.5 32776.0
OUTPUT CODE (DECIMAL)
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MAX11900 16-Bit, 1Msps, Low-Power,
Fully Differential SAR ADC
Typical Operating Characteristics (continued)
(VAVDD = 1.8V, VDVDD = 1.8V, VOVDD = 1.8V, VREFVDD = 3.6V, fSAMPLE = 1Msps, VREF = 3.3V, Internal Ref Buffer On, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
OUTPUT NOISE HISTOGRAM OUTPUT NOISE HISTOGRAM
320000 4 SAMPLES AVERAGE toc13 240000 16 SAMPLES AVERAGE toc14
STDEV = 0.09 LSB STDEV = 0.05 LSB
280000
200000
NUMBER OF OCCURRENCES 11228260400000000000000000000 NUMBER OF OCCURRENCES 1148260000000000000000
40000
0 0
32772.0 32772.5 32773.0 OU32773.5TPUT COD32774.0E (DECIM32774.5AL) 32775.0 32775.5 32776.0 32772.0 32772.5 32773.0 OU32773.5TPUT CO32774.0DE (DECIM32774.5AL) 32775.0 32775.5 32776.0
SNR AND SINAD vs. TEMPERATURE SFDR AND THD vs. TEMPERATURE
100 toc17 135 toc18
SNR -THD
99 133
SINAD SFDR
98 131
SNR AND SINAD (dB) 9999934567 SFDR AND THD (dB)111112222213579
92 119
91 117
90 115
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) TEMPERATURE (°C)
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