Maria-Alexandra PAUN, PhD

20 Pages·2014·0.62 MB·English

by  Maria Paun

OOOOnnnn tttthhhheeee mmmmooooddddeeeelllliiiissssaaaattttiiiioooonnnn ooooffff tttthhhheeee mmmmaaaaiiiinnnn cccchhhhaaaarrrraaaacccctttteeeerrrriiiissssttttiiiiccccssss ooooffff
SSSSOOOOIIII HHHHaaaallllllll cccceeeellllllllssss bbbbyyyy tttthhhhrrrreeeeeeee----ddddiiiimmmmeeeennnnssssiiiioooonnnnaaaallll pppphhhhyyyyssssiiiiccccaaaallll
ssssiiiimmmmuuuullllaaaattttiiiioooonnnnssss
Maria-Alexandra PAUN, PhD
Visiting Researcher
High VoltageMicroelectronics and Sensors (HVMS) Group, Department of
Engineering, University of Cambridge, United Kingdom
Secretary, IEEE Switzerland ExCom
Chair, IEEE WIE Switzerland
Maria-Alexandra Paun - CAM
OUTLINE
(cid:1)
Different Hall cells configurations have been integrated in bulk CMOS
technology and analyzed in terms of their specific parameters.
(cid:1)
A selection of these shapes will be also integrated in a CMOS SOI
technology.
(cid:1)
Geometry plays an important role in Hall cells performance, the
optimum cell is presented in this work.
(cid:1)
The most important parameters of a specific Hall cell, based on SOI
structure, are evaluated through three-dimensional physical
simulations.
2
Maria-Alexandra Paun - CAM
Hall Effect Sensors
A
Ibias
D B
VHall
t
y
B
C
(1) V = S B z x S Gr
S = H I (2)
HALL A
A bias
W nqt
(cid:1)
low-power applications
(cid:1)
current sensing
(cid:1)
position detection & contactless switching
3
Maria-Alexandra Paun - CAM
Hall Cells Design Selection
.
(cid:1)
Different 3D Hall sensors were integrated in bulk CMOS.
(cid:1)
They are all symmetrical and orthogonal structures.
(cid:1)
The geometry plays an important role in the sensors performance.
16  π L  8  π L  θ2 
G ≅ 1− exp−  1− exp−  1− H  (3)
  
π2  2 W  9  2 W  3 
valid if and
0.85 ≤ L /W < ∞ 0 ≤θ ≤ 0.45
H
4
Maria-Alexandra Paun - CAM
Hall Effect Sensors Measurements
(cid:1)
Measurements results on nine different Hall Effect sensors
(cid:1)
Strict project specifications to be met
°
Objectives: offset @ T=300 K < ±30 µµµµT & offset drift < ±0.3 µµµµT/ C
5
Maria-Alexandra Paun - CAM
Single Phase and Residual Offset
(cid:1)
Cell polarization and the corresponding phases
Phases Ibias V
HALL
Phase 1 a to c b to d
Phase 2 d to b a to c
Phase 3 c to a d to b
Phase 4 b to d c to a
(cid:1)
Single phase offset and residual offset
(4)
V = V (B) + V
out HALL offset
V −V +V −V
Offset = P1 P2 P3 P4
(5)
residual (4 phase)
4
6
Maria-Alexandra Paun - CAM
Offset Measurements of bulk CMOS Hall sensors
(cid:1)
An AC automated measurement setup was used to test the Hall structures.
(cid:1)
Manual phase switching was used in the case of temperature investigation.
(cid:1)
Experimental data presented for XL Hall cell (regular bulk CMOS technology).
0.0002
XL
0.00015
0.0001
-5
5 10
0
-5
-5 10
-0.0001 cell4 cell20
cell5 cell21
-0.00015 cell12 cell28
cell13 cell29
-0.0002
0 0.01 0.02 0.03 0.04 0.05 0.06
Sensitivity (V/T) Residual offset vs. temperature for XL cell
Residual offset vs. sensitivity for XL cell
7
Maria-Alexandra Paun - CAM
Regular bulk vs. SOI CMOS technology
The sensors fabricated in SOI (Silicon On Insulator) technology have
obvious benefits, with respect to the bulk Hall sensors.
(cid:1)
higher magnetic sensitivity
(cid:1)
less noise generation
(cid:1)
possibility to use lower biasing voltage
(cid:1)
smaller leakage current through the dielectric
(cid:1)
enhanced radiation resistance etc.
8
Maria-Alexandra Paun - CAM
SOI CMOS technology
(cid:1)
The stacking of the layers, according to a SOI XFAB XI10 fabrication
process.
(cid:1)
The active silicon layer is found on top of the dielectric buried silicon
oxide (SiO ) layer, which is in its turn found on the silicon substrate, or
2
handle wafer.
DOPING CONCENTRATIONS IN THE SOI HALL CELL FABRICATION
Layer Type Numerical value
Wafer (handle)
Si, p-doped (Boron) 6.5 E+14 cm-3
substrate
Dielectric Buried Silicon Oxide, Si0
2
p-substrate in
Si, p-doped (Boron) 1E+15 cm-3
active Silicon layer
n-well in active
Si, n-doped (Arsenic) 5E+16 cm-3
Silicon layer
9
Maria-Alexandra Paun - CAM
The 3D Simulation of SOI Hall Cells
(cid:1)
The structure follows the SOI XFAB XI10 fabrication process.
(cid:1)
active n-well region: Arsenic doping
(cid:2)
Uniform profile implantation
(cid:2)
5*10+16 cm-3
(cid:1)
electrical contacts
(cid:1)
Handle wafer
OPTIMUM HALL CELL DESIGN FEATURES
Parameter Value
(cid:1)
p-substrate: Boron doping L (µm) 50
(cid:1)
SiO2
concentration of 10+15 cm-3 W (µm) 50
Contacts dimension
4.7
s (µm)
10 The 3D model of Optimum SOI Hall cell