LTC2122 – Dual 14-Bit 170Msps ADC with JESD204B Serial Outputs

50 Pages·2014·0.9 MB·English

by  Linear Technology Corporation

LTC2122
Dual 14-Bit 170Msps ADC
with JESD204B Serial Outputs
FEATURES DESCRIPTION
n 6.0Gbps JESD204B Interface The LTC®2122 is a 2-channel simultaneous sampling
n Only One Output Lane Required for Both ADCs 170Msps 14-bit A/D converter with serial JESD204B
(F < = 150Msps) outputs. It is designed for digitizing high frequency,
S
n 70dBFS SNR wide dynamic range signals. It is perfect for demanding
n 90dBFS SFDR communications applications with AC performance that
n Low Power: 751mW Total includes 70dBFS SNR and 90dBFS spurious free dynamic
n Single 1.8V Supply range (SFDR). The 1.25GHz input bandwidth allows the
n Easy to Drive 1.5V Input Range ADC to under-sample high frequencies.
P-P
n 1.25GHz Full Power Bandwidth S/H
The JESD204B serial interface simplifies the PCB design by
n Optional Clock Divide by Two
minimizing the number of data lines required. At 170Msps,
n Optional Clock Duty Cycle Stabilizer
only two 3.4Gbps output lanes are required. For sample
n Low Power Sleep and Nap Modes
rates up to 150Msps, both ADCs may share the same
n Serial SPI Port for Configuration
output lane at up to 6.0Gbps.
n 48-Lead (7mm × 7mm) QFN Package
The DEVCLK+ and DEVCLK– inputs can be driven differ-
APPLICATIONS
entially with sine wave, PECL, or LVDS signals. An optional
clock divide-by-two circuit or clock duty cycle stabilizer
n Communications
maintains high performance at full speed for a wide range
n Cellular Base Stations
of clock duty cycles.
n Software Defined Radios
n Medical Imaging L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n High Definition Video
n Test and Measurement Instrumentation
TYPICAL APPLICATION
OVDD 64k Point 2-Tone FFT,
1.2V TO 1.9V
f = 71MHz and 69MHz,
LTC2122 IN
–7dBFS, 170Msps
50Ω 50Ω
0
ANALOG JESD204B
INPUT 14-BIT ADC LOGIC SERIALIZER 3.4Gbps
–20
BFS) –40
CLOCK ÷ C2 LOORC K÷ 1 PLL 1.2VO TVOD D1.9V FPGAJE OSRD 2A0S4IBC MPLITUDE (d ––8600
(170MHz OR A
340MHz)
50Ω 50Ω –100
ANALOG JESD204B –120
INPUT 14-BIT ADC LOGIC SERIALIZER 3.4Gbps 0 10 20 30 40 50 60 70 80
FREQUENCY (MHz)
2122 TA01a
2122 TA01
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LTC2122
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Notes 1, 2)
Supply Voltages TOP VIEW
V , OV ......................................................0.3V to 2V
DD DD DDNDSCKDIDO+F–FNDND DDDD
Analog Input Voltage VGCSSSOOGGVV
876543210987
444444444333
A +, A – .......................–0.3V to (V + 0.2V)
INA/B INA/B DD
SENSE (Note 3) ............................–0.3V to (V + 0.2V) VDD 1 36OVDD
DD GND 2 35OVDD
Digital Input Voltage AINA+ 3 34DNC
DEVCLK+, DEVCLK–, SYSREF+, SYSREF–, AINA– 4 33DNC
SENSE 5 32CMLOUT_A0+
SYNC~+, SYNC~– (Note 3) .......–0.3V to (VDD + 0.3V) VREF 6 49 31CMLOUT_A0–
CS, SDI, SCK (Note 4) ..........................–0.3V to 3.9V GVNCMD 78 GND 3209CCMMLLOOUUTT__BB00+–
SDO (Note 4) ............................................–0.3V to 3.9V AINB– 9 28DNC
AINB+10 27DNC
Digital Output Voltage ..................–0.3V to (V + 0.3V)
DD GND11 26OVDD
Operating Ambient Temperature Range VDD12 25OVDD
LTC2122C ................................................0°C to 70°C
345678901234
111111122222
LTC2122I ............................................–40°C to 85°C VDDGND–CLK+CLKGND+REF–REFGND+NC~–NC~VDDVDD
Storage Temperature Range ..................–65°C to 150°C DEVDEV SYSSYS SYSY
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN

TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2122CUK#PBF LTC2122CUK#TRPBF LTC2122UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C
LTC2122IUK#PBF LTC2122IUK#TRPBF LTC2122UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2122
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 5)
A
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) l 14 Bits
Integral Linearity Error Differential Analog Input (Note 6) l –5.1 ±1.2 5.1 LSB
Differential Linearity Error Differential Analog Input l –0.9 ±0.35 0.9 LSB
Offset Error (Note 7) l –13 ±5 13 mV
Gain Error Internal Reference ±1.5 %FS
External Reference l –4.0 ±1 2.2 %FS
Offset Drift ±20 µV/ºC
Full-Scale Drift Internal Reference ±30 ppm/ºC
External Reference ±10 ppm/ºC
Transition Noise 1.82 LSB
RMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V Analog Input Range (A + – A –) 1.7V < V < 1.9V l 1.5 V
IN IN IN DD P-P
V Analog Input Common Mode (A + + A –)/2 Differential Analog Input (Note 8) l V – 20mV V V + 20mV V
IN(CM) IN IN CM CM CM
V External Voltage Reference Applied to SENSE External Reference Mode l 1.2 1.250 1.3 V
SENSE
I Analog Input Leakage Current 0 < A +, A – < V , No Clock l –1 1 µA
IN1 IN IN DD
I SENSE Input Leakage Current 1.2V < SENSE < 1.3V l –1 1 µA
IN2
t Sample-and-Hold Acquisition Delay Time 1 ns
AP
t Sample-and-Hold Acquisition Delay Jitter 0.15 ps
JITTER RMS
CMRR Analog Input Common Mode Rejection Ratio 75 dB
BW–3dB Full-Power Bandwidth 1250 MHz
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 15MHz Input 70 dBFS
70MHz Input 69.8 dBFS
140MHz Input l 67.7 69.1 dBFS
SFDR Spurious Free Dynamic Range 2nd or 3rd 15MHz Input 90 dBFS
Harmonic 70MHz Input 85 dBFS
140MHz Input l 76 80 dBFS
Spurious Free Dynamic Range 4th Harmonic 15MHz Input 95 dBFS
or Higher 70MHz Input 95 dBFS
140MHz Input l 83 85 dBFS
S/(N+D) Signal-to-Noise Plus Distortion Ratio 15MHz Input 69.9 dBFS
70MHz Input 69.4 dBFS
140MHz Input l 67.3 68.5 dBFS
Crosstalk Crosstalk Between Channels Up to 250MHz Input –90 dB
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LTC2122
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 5)
A
PARAMETER CONDITIONS MIN TYP MAX UNITS
V Output Voltage I = 0 0.435 • 0.435 • 0.435 • V
CM OUT
V – 18mV V V + 18mV
DD DD DD
V Output Temperature Drift ±37 ppm/°C
CM
V Output Resistance –1mA < I < 1mA 4 Ω
CM OUT
V Output Voltage I = 0 1.225 1.250 1.275 V
REF OUT
V Output Temperature Drift ±30 ppm/°C
REF
V Output Resistance –400µA < I < 1mA 7 Ω
REF OUT
V Line Regulation 1.7V < V < 1.9V 0.6 mV/V
REF DD
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V Analog Supply Voltage Single-Lane Operation l 1.8 1.85 1.9 V
DD
Two-Lane Operation l 1.7 1.8 1.9 V
OV Output Supply Voltage CML Current = 16mA, Directly Terminated (Note 8) l 1.2 1.9 V
DD
CML Current = 16mA, AC Terminated l 1.4 1.9 V
I Analog Supply Current l 417 459 mA
VDD
I Output Supply Current Per Lane CML Current = 12mA l 11 12 13.8 mA
OVDD
P Power Dissipation V = 1.8V, Excluding OV Power l 751 826 mW
DISS DD DD
P Sleep Mode Power 2 mW
SLEEP
P Nap Mode Power 433 mW
NAP
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CLOCK INPUTS (DEVCLK+, DEVCLK–)
V Differential Input Voltage (Note 8) l 0.2 V
ID
V Common Mode Input Voltage Internally Set 1.2 V
ICM
Externally Set (Note 8) l 1.1 1.5 V
R Input Resistance (See Figure 2) 10 kΩ
IN
C Input Capacitance 2 pF
IN
Differential Digital Inputs (SYNC~+, SYNC~–, SYSREF+, SYSREF–)
V Differential Input Voltage (Note 8) l 0.2 V
ID
V Common Mode Input Voltage Internally Set 1.2 V
ICM
Externally Set (Note 8) l 1.1 1.5 V
R Input Resistance 6.7 kΩ
IN
C Input Capacitance 2 pF
IN
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LTC2122
DIGITAL INPUTS AND OUTPUTS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (CS, SDI, SCK)
V High Level Input Voltage V = 1.8V l 1.3 V
IH DD
V Low Level Input Voltage V = 1.8V l 0.6 V
IL DD
I Input Current V = 0V to 3.6V l –10 10 µA
IN IN
C Input Capacitance (Note 8) 3 pF
IN
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
R Logic Low Output Resistance to GND V = 1.8V, SDO = 0V 200 Ω
OL DD
I Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 µA
OH
C Output Capacitance (Note 8) 4 pF
OUT
LVDS OUTPUTS (OF+, OF–)
V Differential Output Voltage 100Ω Differential Load l 247 350 454 mV
OD
V Common Mode Output Voltage l 1.125 1.25 1.375 V
OS
CML Outputs
V CML Differential Output Voltage Output Current Set to 10mA 500 mVppd
DIFF
Output Current Set to 12mA 600 mVppd
Output Current Set to 14mA 700 mVppd
Output Current Set to 16mA 800 mVppd
V Output High Level Directly-Coupled 50Ω to OV OV V
OH DD DD
Directly-Coupled 100Ω Differential OV -1/4 V V
DD DIFF
AC-Coupled OV -1/4 V V
DD DIFF
V Output Low Level Directly-Coupled 50Ω to OV OV -1/2 V V
OL DD DD DIFF
Directly-Coupled 100Ω Differential OV -3/4 V V
DD DIFF
AC-Coupled OV -3/4 V V
DD DIFF
V Output Common Mode Level Directly-Coupled 50Ω to OV OV -1/4 V V
OCM DD DD DIFF
Directly-Coupled 100Ω Differential OV -1/2 V V
DD DIFF
AC-Coupled OV -1/2 V V
DD DIFF
R Output Resistance Single-Ended 50 Ω
OUT
Differential l 80 100 120 Ω
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f , 1/t Sampling Frequency (Note 9) l 50 170 MHz
S S
t 1× CLK Low Time (Note 8) Duty Cycle Stabilizer Off l 2.79 2.94 10 ns
L
Duty Cycle Stabilizer On l 1.5 2.94 10 ns
t 1× CLK High Time (Note 8) Duty Cycle Stabilizer Off l 2.79 2.94 10 ns
H
Duty Cycle Stabilizer On l 1.5 2.94 10 ns
t DEVCLK Period 2X_CLK SPI Register = 0 l 5.88 20 ns
DCK
2X_CLK SPI Register = 1 l 2.94 10 ns
SPI Port Timing (Note 8)
t SCK Period Write Mode l 40 ns
SCK
Readback Mode C = 20pF, R = 2k l 250 ns
SDO PULLUP
t CS to SCK Set-Up Time l 5 ns
CSS
t SCK to CS Hold Time l 5 ns
CSH
t SDI Set-Up Time l 5 ns
DS
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LTC2122
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 5)
A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t SDI Hold Time l 5 ns
DH
t SCK Falling to SDO Valid Readback Mode C = 20pF, R = 2K l 125 ns
DO SDO PULLUP
JESD204B Timing (Note 8)
t High Speed Serial Bit Period 1 Lane Mode (2 ADC to One Lane) l 167 1000 ps
BIT, UI
2 Lane Mode (1 Lane Per ADC) l 294 1000 ps
t Total Jitter of CML Outputs (P-P) > 3.125Gbps Per Lane (BER = 1E-15, Note 8) l 0.3 UI
JIT
< = 3.125Gbps Per Lane (BER = 1E-12, Note 8) l 0.35 UI
t SYNC~ to CLK Set-Up Time (Note 8) l 0.6 ns
SU_SYN
t DEVCLK to SYNC~ Hold Time (Note 8) l 0.6 ns
H_SYN
t SYSREF to DEVCLK Set-Up Time (Note 8) l 0.2 (t – 0.32) ns
SU_SYS DCK
t DEVCLK to SYSREF Hold Time (Note 8) l 0.32 ns
H_SYS
LAT Pipeline Latency, Single-Lane Mode (Note 10) l 10.5 10.5 t
P1 S
LAT Pipeline Latency, 2-Lane Mode (Note 10) l 13.5 13.5 t
P2 S
t Delay from DEVCLK to Serial Data Out (Note 8) l 0.6 t
DS S
LAT Latency from SYNC~ Assertion to COMMA (Note 10) l 7 7 t
SC1 S
Out, Single Lane Mode
LAT Latency from SYNC~ Assertion to COMMA (Note 10) l 10 10 t
SC2 S
Out, 2-Lane Mode
LAT Latency from SYNC~ De-assertion to LAS (Note 10, 11) l 3 3 t
SL1 S
Out, Single-Lane Mode
LAT Latency from SYNC~ De-assertion to LAS (Note 10, 11) l 6 6 t
SL2 S
Out, 2-Lane Mode
LAT Overflow Latency (Note 10) l 6 6 t
OF S
t Analog Delay of OF with 1X_CLK (Note 8) l 1.4 1.7 2.0 ns
D_OF1X
t Analog Delay of OF with 2X_CLK (Note 8) l 1.6 1.9 2.2 ns
D_OF2X
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Integral nonlinearity is defined as the deviation of a code from a
may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from
Maximum Rating condition for extended periods may affect device the center of the quantization band.
reliability and lifetime. Note 7: Offset error is the offset voltage measured from –0.5LSB when the
Note 2: All voltage values are with respect to GND (unless otherwise noted). output code flickers between 01 1111 1111 1111 and 10 0000 0000 0000.
Note 3: When these pin voltages are taken below GND or above VDD, they Note 8: Guaranteed by design, not subject to test.
will be clamped by internal diodes. This product can handle input currents
Note 9: Recommended operating conditions.
of greater than 100mA below GND or above V without latchup.
DD Note 10: When the “2×_CLK” SPI register bit is set, the DEVCLK
Note 4: When these pin voltages are taken below GND they will be
frequency is 2× the sampling frequency. When the “2×_CLK” bit is not
clamped by internal diodes. When these pin voltages are taken above V
DD set, the DEVCLK frequency is equal to the sampling frequency. Latency is
they will not be clamped by internal diodes. This product can handle input
measured in units of sampling periods (t ), where t is the inverse of the
currents of greater than 100mA below GND without latchup. S S
sampling frequency.
Note 5: V = 1.8V, f = 170MHz, differential DEVCLK+/DEVCLK– =
DD SAMPLE Note 11: When in subclass 0, the Lane Alignment Sequence (LAS) latency
2V sine wave, input range = 1.5V with differential drive, unless
P-P P-P measurement begins at the start of the frame following the detection
otherwise noted.
of SYNC~ de-assertion. When in subclasses 1 or 2 this LAS latency
measurement begins at the start of the first multiframe following the
detection of SYNC~ de-assertion.
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LTC2122
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL) AC Grounded Input Histogram
2.0 1.00 30000
1.5 0.75
25000
1.0 0.50
INL ERROR (LSB) –000...505 DNL ERROR (LSB) –000...202505 COUNT 211050000000000
–1.0 –0.50
5000
–1.5 –0.75
–2.0 –1.00 0
0 4096 8192 12288 16384 0 4096 8192 12288 16384 8192 8195 8198 8201 8204 8207
OUTPUT CODE
OUTPUT CODE OUTPUT CODE
2122 G01 2122 G02 2122 G03
64k Point FFT, f = 15.0MHz, 64k Point FFT, f = 69.8MHz, 64k Point FFT, f = 140.0MHz,
IN IN IN
–1dBFS, 170Msps –1dBFS, 170Msps –1dBFS, 170Msps
0 0 0
–20 –20 –20
S) –40 S) –40 S) –40
BF BF BF
d d d
E ( E ( E (
D –60 D –60 D –60
U U U
T T T
LI LI LI
P P P
M –80 M –80 M –80
A A A
–100 –100 –100
–120 –120 –120
0 20 40 60 80 0 20 40 60 80 0 20 40 60 80
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2122 G04 2122 G05 2122 G06
64k Point FFT, f = 185.1MHz, 64k Point FFT, f = 223.1MHz, 64k Point FFT, f = 383.1MHz,
IN IN IN
–1dBFS, 170Msps –1dBFS, 170Msps –1dBFS, 170Msps
0 0 0
–20 –20 –20
S) –40 S) –40 S) –40
BF BF BF
d d d
E ( E ( E (
D –60 D –60 D –60
U U U
T T T
LI LI LI
P P P
M –80 M –80 M –80
A A A
–100 –100 –100
–120 –120 –120
0 20 40 60 80 0 20 40 60 80 0 20 40 60 80
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2122 G07 2122 G08 2122 G09
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LTC2122
TYPICAL PERFORMANCE CHARACTERISTICS
64k Point FFT, f = 421.1MHz, 64k Point FFT, f = 567.0MHz, 64k Point FFT, f = 907.0MHz
IN IN IN
–1dBFS, 170Msps –1dBFS, 170Msps –1dBFS, 170Msps
0 0 0
–20 –20 –20
S) –40 S) –40 S) –40
F F F
B B B
d d d
E ( E ( E (
D –60 D –60 D –60
U U U
T T T
LI LI LI
P P P
M –80 M –80 M –80
A A A
–100 –100 –100
–120 –120 –120
0 20 40 60 80 0 20 40 60 80 0 20 40 60 80
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2122 G10 2122 G11 2122 G12
64k Point 2-Tone FFT, f = 71MHz SFDR vs Input Level, f = 70MHz, SNR vs Input Level, f = 70MHz,
IN IN IN
and 69MHz, –7dBFS, 170Msps 1.5V Range, 170Msps 1.5V Range, 170Msps
0 120 80
110
70
–20 100 dBFS
dBFS
AMPLITUDE (dBFS) –––864000 SFDR (dBc AND dBFS) 43658790000000 dBc SNR (dBc AND dBFS) 2436500000 dBc
–100 20
10
10
–120 0 0
0 10 20 30 40 50 60 70 80 –80 –70 –60 –50 –40 –30 –20 –10 0 –70 –60 –50 –40 –30 –20 –10 0
FREQUENCY (MHz) INPUT LEVEL (dBFS) INPUT LEVEL (dBFS)
2122 G13 2122 G14 2122 G15
SFDR vs Input Frequency, SNR vs Input Frequency, I vs Sample Rate,
VDD
–1dBFS, 1.5V Range, 170Msps –1dBFS, 1.5V Range, 170Msps f = 15MHz, –1dBFS
IN
90 75 440
70 420
85
65 400
80
SFDR (dBFS) 75 SNR (dBFS) 6505 I (mA) VDD 336800 2 LANE 1 LANE
70
50 340
65
45 320
60 40 300
0 200 400 600 800 1000 0 200 400 600 800 1000 40 60 80 100 120 140 160 180
INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) SAMPLE RATE (Msps)
2122 G16 2122 G17 2122 G18
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LTC2122
TYPICAL PERFORMANCE CHARACTERISTICS
CMLOUT Bathtub Curve, 3.4Gbps CMLOUT Eye Diagram, 3.4Gbps
1E-01
1E-03
R)
BE1E-05
RATE (1E-07 V/DIV
RROR 1E-09 100m
E
T
BI1E-11
1E-13
1E-15
0.0 0.2 0.4 0.6 0.8 1.0 49.0ps/DIV
2122 G20
UNIT INTERVAL (UI)
2122 G19
CMLOUT Eye Diagram,
CMLOUT Bathtub Curve, 6.0Gbps 6.0Gbps Single Lane
1E-01
1E-03
R)
BE1E-05
R RATE (1E-07 mV/DIV
RO1E-09 00
R 1
E
T
BI1E-11
1E-13
1E-15
0.0 0.2 0.4 0.6 0.8 1.0 27.8ps/DIV
UNIT INTERVAL (UI) 2122 G22
2122 G21
CMLOUT Eye Diagram, 6.0Gbps,
Single Lane, 8in (20cm) FR4
V
DI
V/
m
0
0
1
27.8ps/DIV
2122 G23
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LTC2122
PIN FUNCTIONS
V (Pins 1, 12, 13, 23, 24, 37, 38, 48): 1.8V Power In subclass 2 a low to high transition of SYNC~ is sampled
DD
Supply. Bypass to ground with 0.1µF ceramic capacitors. on the rising edge of DEVCLK to reset the internal dividers
Adjacent pins can share bypass capacitor. and set up deterministic latency.
GND (Pins 2, 8, 11, 14, 17, 20, 39, 40, 47, Exposed Pad OV (Pins 25, 26, 35, 36): 1.2V to 1.9V Output Driver
DD
Pin 49): Device Power Ground. The exposed pad must be Supply. Bypass each pair to ground with 0.1μF ceramic
soldered to the PCB ground. capacitors.
A +/A –(Pins 3, 4): Analog Input Pair for Channel A. CMLOUT_B0–/CMLOUT_B0+ (Pins 29, 30): Current Mode
INA INA
Logic Output Pair for Channel B in two lane mode. Must
SENSE (Pin 5): Reference Programming Pin. Connecting
be terminated with a 50Ω resistor to OV , a differential
SENSE to V selects the internal reference and a ±0.75V DD
DD
100Ω resistor to the complementary output, or AC coupled
input range. An external reference between 1.2V and 1.3V
to another termination voltage.
applied to SENSE selects an input range of ±0.6 × V .
SENSE
CMLOUT_A0–/CMLOUT_A0+ (Pins 31, 32): Current Mode
V (Pin 6): Reference Voltage Output. Bypass to ground
REF
Logic Output Pair for Channel A in two lane mode or for
with a 2.2μF ceramic capacitor. Nominally 1.25V.
both Channel A and Channel B in one lane mode. Must
VCM (Pin 7): Common Mode Bias Output. Nominally equal be terminated with a 50Ω resistor to OVDD, a differential
to 0.435 • VDD. VCM should be used to bias the common 100Ω resistor to the complementary output, or AC coupled
mode of the analog inputs. Bypass to ground with a 0.1μF to another termination voltage.
ceramic capacitor.
OF–/OF+ (Pins 41, 42): Over/Underflow LVDS Digital
AINB–/AINB+ (Pins 9, 10): Analog Input Pair for Channel B. Output. OF is high when an overflow or underflow has
DEVCLK–/DEVCLK+ (Pins 15, 16): Device Clock Input Pair. occurred. The overflows for channel A and channel B are
multiplexed together and transmitted at twice the sample
The sample clock is derived from this clock signal. In
frequency (OF = OF+ – OF–).
divide-by-one mode, the analog signal is sampled on the
falling edge of DEVCLK (DEVCLK = DEVCLK+ – DEVCLK–). SDO (Pin 43): Serial Interface Data Output. SDO is the
optional serial interface data output. Data on SDO is read
DEVCLK may optionally be divided by two. In subclass 1
back from the mode control registers and can be latched
a low to high transition of the SYSREF signal will initialize
on the falling edge of SCK. SDO is an open-drain N-channel
the divide-by-two circuit on the rising edge of DEVCLK. In
MOSFET output that requires an external 2k pull-up resis-
Subclass 2 a low to high transition of the SYNC~ signal
tor from 1.8V to 3.3V. If readback from the mode control
will initialize the divide-by-two circuit on the rising edge
registers is not needed, the pull-up resistor is not neces-
of DEVCLK.
sary and SDO can be left unconnected.
SYSREF+/SYSREF– (Pins 18, 19): A JESD204B Subclass
SDI (Pin 44): Serial Interface Data Input. SDI is the serial
1 Input Signal Pair. A low to high transition of SYSREF is
interface data input. Data on SDI is clocked into the mode
sampled on the rising edge of DEVCLK to reset the inter-
control registers on the rising edge of SCK. SDI can be
nal dividers and set up deterministic latency (SYSREF =
SYSREF+ – SYSREF–). driven with 1.8V to 3.3V logic.
SYNC~+/SYNC~– (Pins 21, 22): A JESD204B Synchroniza- SCK (Pin 45): Serial Interface Clock Input. SCK is the
serial interface clock input. SCK can be driven with 1.8V
tion Input Signal Pair. Used to establish initial Code-Group
to 3.3V logic.
synchronization for all three subclasses. A low level of
the SYNC~ signal causes the LTC2122 to output K28.5 CS (Pin 46): Serial Interface Chip Select Input. When CS is
commas (SYNC~ = SYNC~+ – SYNC~–). low, SCK is enabled for shifting data on SDI into the mode
control registers. CS can be driven with 1.8V to 3.3V logic.
2122fa
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