Low-Power Stereo ADC for Wireless Handsets - Texas Instruments

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TLV320ADC3101
SLAS553B–NOVEMBER2008–REVISEDAUGUST2015
TLV320ADC3101 Low-Power Stereo ADC With Embedded miniDSP
for Wireless Handsets and Portable Audio
1 Features 2 Applications
• StereoAudioADC • WirelessHandsets
1
– 92-dBASignal-to-NoiseRatio • PortableLow-PowerAudioSystems
– SupportsADCSampleRatesFrom8kHzto • Noise-CancellationSystems
96kHz • Front-EndVoiceorAudioProcessorfor Digital
• Instruction-ProgrammableEmbeddedminiDSP Audio
• FlexibleDigitalFilteringWithRAMProgrammable
3 Description
Coefficient,Instructions,andBuilt-InProcessing
Blocks The TLV320ADC3101 device is a low-power, stereo
audio analog-to-digital converter (ADC) supporting
– Low-LatencyIIRFiltersforVoice
sampling rates from 8 kHz to 96 kHz with an
– LinearPhaseFIRFiltersforAudio integrated programmable-gain amplifier providing up
– AdditionalProgrammableIIRFiltersforEQ, to 40-dB analog gain or AGC. A programmable
NoiseCancellationorReduction miniDSP is provided for custom audio processing.
Front-end input coarse attenuation of 0 dB, –6 dB, or
– Upto128ProgrammableADCDigital Filter
off, is also provided. The inputs are programmable in
Coefficients
a combination of single-ended or fully differential
• SixAudioInputsWithConfigurableAutomatic configurations. Extensive register-based power
GainControl(AGC) control is available via an I2C interface, enabling
– ProgrammableinSingle-EndedorFully mono or stereo recording. Low power consumption
makes the TLV320ADC3101 ideal for battery-
DifferentialConfigurations
poweredportableequipment.
– CanBe3-StatedforEasyInteroperabilityWith
OtherAudioICs DeviceInformation(1)
• LowPowerConsumptionandExtensiveModular
PARTNUMBER PACKAGE BODYSIZE(NOM)
PowerControl:
TLV320ADC3101 VQFN(24) 4.00mm×4.00mm
– 6-mWMonoRecord,8-kHz
(1) For all available packages, see the orderable addendum at
– 11-mWStereoRecord,8-kHz theendofthedatasheet.
– 10-mWMonoRecord,48-kHz
FunctionalBlockDiagram
– 17-mWStereoRecord,48-kHz
• DualProgrammableMicrophoneBias Processor
• ProgrammablePLLforClockGeneration
• I2CControlBus
I2C I2S, LJ, RJ, DSP, TDM
• AudioSerialDataBusSupportsI2S,Left/Right-
Justified, DSP,PCM,andTDMModes ADC
• DigitalMicrophoneInputSupport miniDSP
• TwoGPIOs
ADC
• PowerSupplies:
– Analog:2.6Vto3.6V Digital Mic
– Digital:Core:1.65Vto1.95V,
TLV320ADC3101
I/O:1.1V–3.6V
• 4-mm×4-mm24-PinRGE(VQFN)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TLV320ADC3101
SLAS553B–NOVEMBER2008–REVISEDAUGUST2015 www.ti.com
Table of Contents
1 Features.................................................................. 1 10 DetailedDescription........................................... 12
2 Applications........................................................... 1 10.1 Overview...............................................................12
3 Description............................................................. 1 10.2 FunctionalBlockDiagram.....................................13
4 RevisionHistory..................................................... 2 10.3 FeatureDescription...............................................13
10.4 DeviceFunctionalModes......................................41
5 Description(continued)......................................... 3
10.5 Programming.........................................................42
6 DeviceComparisonTable..................................... 3
10.6 RegisterMaps.......................................................43
7 PinConfigurationandFunctions......................... 4
11 ApplicationandImplementation........................ 78
8 Specifications......................................................... 5
11.1 ApplicationInformation..........................................78
8.1 AbsoluteMaximumRatings......................................5
11.2 TypicalApplication ...............................................78
8.2 ESDRatings..............................................................5
12 PowerSupplyRecommendations..................... 82
8.3 RecommendedOperatingConditions.......................5
13 Layout................................................................... 83
8.4 ThermalInformation..................................................6
13.1 LayoutGuidelines.................................................83
8.5 ElectricalCharacteristics...........................................6
13.2 LayoutExample....................................................83
8.6 DissipationRatings ..................................................7
8.7 I2S/LJF/RJFTiminginMasterMode.........................8 14 DeviceandDocumentationSupport................. 84
8.8 DSPTiminginMasterMode.....................................8 14.1 CommunityResources..........................................84
8.9 I2S/LJF/RJFTiminginSlaveMode...........................8 14.2 Trademarks...........................................................84
8.10 DSPTiminginSlaveMode.....................................8 14.3 ElectrostaticDischargeCaution............................84
8.11 TypicalCharacteristics..........................................11 14.4 Glossary................................................................84
9 ParameterMeasurementInformation................11 15 Mechanical,Packaging,andOrderable
Information........................................................... 84
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionA(September2009)toRevisionB Page
• AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional
Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device
andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1
ChangesfromOriginal(November2008)toRevisionA Page
• RevisedcolumnheadingforPinFunctionstable................................................................................................................... 4
• AddedvoltagevalueforAVDDinElectricalCharacteristicsconditionstatement.................................................................. 6
• Added"Inputcommon-modevoltage"toADCElectricalCharacteristicsTable..................................................................... 6
• AddedvoltagevalueforAVDDinElectricalCharacteristicsconditionstatement.................................................................. 7
• AddedarowtotheMicrophoneBiassectionoftheElectricalCharacteristicstable............................................................. 7
• ChangedFigure4-DSPTiminginSlaveMode.AddedtheWCLKtextnote..................................................................... 10
• ChangedFigure9-Single-EndedDynamicRangePlottoInput-ReferredNoisevsPGAGain......................................... 11
• ChangedRevisedblockdiagram.......................................................................................................................................... 13
• AddedminiDSPSectionandminiDSPInformationThroughoutDatasheet......................................................................... 14
• AddedFigure40-2sComplementCoefficientFormat........................................................................................................ 35
• ChangedDataFormatforAllControlRegisterDefinitionsFromDecimalToHex(Binary) ................................................ 43
• Removednotefollowingthepage0/register94descriptiontable..................................................................................... 62
• Changedbitvaluesfrom1and2to0and1,respectively................................................................................................... 62
• Listedvalues81through127asreserved........................................................................................................................... 62
• Replacedthelistingofpage4registers............................................................................................................................... 69
• Addedalistingforpage5registers...................................................................................................................................... 73
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5 Description (continued)
TheAGCprogramstoawiderangeofattack(7msto1.4s)anddecay(50msto22.4s)times.Aprogrammable
noise-gate function is included to avoid noise pumping. Low-latency IIR filters optimized for voice and telephony
are available, as well as linear-phase FIR filters optimized for audio. Programmable IIR filters are also available
and may be used for sound equalization, or to remove noise components. The audio serial bus can be
programmed to support I2S, left-justified, right-justified, DSP, PCM, and TDM modes. The audio bus may be
operatedineithermasterorslavemode.
A programmable integrated PLL is included for flexible clock generation and provides support for all standard
audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, including the most popular
casesof12-MHz,13-MHz,16-MHz,19.2-MHz,and19.68-MHzsystem clocks.
6 Device Comparison Table
FEATURES TLV320ADC3101 TLV320ADC3001
NumberofADCs 2 2
NumberofInputs/Outputs 6/DigitalI/F 3/DigitalI/F
Resolution(Bits) 24 24
ControlInterface I2C I2C
DigitalAudioInterface LJ,RJ,I2S,DSP,TDM LJ,RJ,I2S,DSP,TDM
DigitalMicrophoneSupport Yes No
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7 Pin Configuration and Functions
RGEPackage
24-PinVQFNWithExposedThermalPad
TopView
O2 O1
PI PI
G G
D K/ N/
CLK VSS VDD OD MCL MDI
M D D V D D
I
4 3 2 1 0 9
2 2 2 2 2 1
BCLK 1 18 SDA
WCLK 2 17 SCL
DOUT 3 16 I2C_ADR1
RESET 4 15 I2C_ADR0
MICBIAS1 5 14 MICBIAS2
IN3L(M) 6 13 IN3R(M)
7 8 9 10 11 12
L(P) L(P) VSS VDD R(M) R(P)
N2 N1 A A N1 N2
I I I I
ConnecttheVQFNthermalpadtoAVSS.
PinFunctions
PIN
TYPE DESCRIPTION
NAME NO.
AVDD 10 P Analogvoltagesupply,2.6V–3.6V
AVSS 9 P Analoggroundsupply,0V
BCLK 1 I/O Audioserialdatabusbitclock(input/output)
Digitalmicrophoneclock/general-purposeinput/output2(input/output)/PLLclockinput/
DMCLK/GPIO2 20 I/O audioserialdata-busbit-clockinput/output/multifunctionpinbasedonregister
programming
Digitalmicrophonedatainput/general-purposeinput/output1(input/output)/PLLclock
DMDIN/GPIO1 19 I/O
muxoutput/AGCnoiseflag/multifunctionpinbasedonregisterprogramming
DOUT 3 O Audioserialdatabusdataoutput(output)
DVDD 22 P Digitalcorevoltagesupply,1.65V–1.95V
DVSS 23 P Digitalgroundsupply,0V
I2C_ADR0 15 I LSBofI2Cbusaddress
I2C_ADR1 16 I LSB+1ofI2Cbusaddress
IN1L(P) 8 I Micorlineanaloginput(left-channelsingle-endedordifferentialplus,orrightchannel)
IN1R(M) 11 I Micorlineanaloginput(left-channelsingle-endedordifferentialminus,orleftchannel)
IN2L(P) 7 I Micorlineanaloginput(left-channelsingle-endedordifferentialplus)
IN2R(P) 12 I Micorlineanaloginput(right-channelsingle-endedordifferentialplus)
IN3L(M) 6 I Micorlineanaloginput(left-channelsingle-endedordifferentialminus)
IN3R(M) 13 I Micorlineanaloginput(right-channelsingle-endedordifferentialminus)
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PinFunctions (continued)
PIN
TYPE DESCRIPTION
NAME NO.
IOVDD 21 P I/Ovoltagesupply,1.1V–3.6V
MCLK 24 I Masterclockinput
MICBIAS1 5 O MICBIAS1biasvoltageoutput
MICBIAS2 14 O MICBIAS2biasvoltageoutput
RESET 4 I Reset
SCL 17 I/O I2Cserialclock
SDA 18 I/O I2Cserialdatainput/output
WCLK 2 I/O Audioserialdatabuswordclock(input/output)
8 Specifications
8.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) (2)
MIN MAX UNIT
AVDDtoAVSS –0.3 3.9 V
IOVDDtoDVSS –0.3 3.9 V
DVDDtoDVSS –0.3 2.5 V
DigitalinputvoltagetoDVSS –0.3 IOVDD+0.3 V
AnaloginputvoltagetoAVSS –0.3 AVDD+0.3 V
Operatingtemperature –40 85 °C
T Max Junctiontemperature 105 °C
J
Powerdissipation (T Max–T )/θ W
J A JA
T Storagetemperature –65 125 °C
stg
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2) ESDcomplacencetestedtoEIA/JESD22-A114-Bandpassed.
8.2 ESD Ratings
VALUE UNIT
Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1000
V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- ±250 V
C101(2)
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
8.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) Analogsupplyvoltage 2.6 3.3 3.6 V
DVDD(1) Digitalcoresupplyvoltage 1.65 1.8 1.95 V
IOVDD(1) DigitalI/Osupplyvoltage 1.1 1.8 3.6 V
V Analogfull-scale0-dBinputvoltage(AVDD=3.3V) 0.707 Vrms
I
Digitaloutputloadcapacitance 10 pF
T Operatingfree-airtemperature –40 85 °C
A
(1) AnalogvoltagevaluesarewithrespecttoAVSS;digitalvoltagevaluesarewithrespecttoDVSS.
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8.4 Thermal Information
TLV320ADC3101
THERMALMETRIC(1) RGE(VQFN) UNIT
24PINS
R Junction-to-ambientthermalresistance 33.9 °C/W
θJA
R Junction-to-case(top)thermalresistance 34.1 °C/W
θJC(top)
R Junction-to-boardthermalresistance 11.5 °C/W
θJB
ψ Junction-to-topcharacterizationparameter 0.4 °C/W
JT
ψ Junction-to-boardcharacterizationparameter 11.5 °C/W
JB
R Junction-to-case(bottom)thermalresistance 3.2 °C/W
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report,SPRA953.
8.5 Electrical Characteristics
At25°C,AVDD=3.3V,IOVDD=1.8V,DVDD=1.8V,f =48-kHz,16-bitaudiodata(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
AUDIOADC
Inputsignallevel(0-dB) Single-endedinput 0.707 Vrms
Inputcommon-modevoltage Single-endedinput 1.35 Vrms
Signal-to-noiseratio, f =48kHz,0-dBPGAgain,IN1inputsselected
SNR S 80 92 dB
A-weighted(1) (2) andAC-shortedtoground
Dynamicrange, f =48kHz,1-kHz–60-dBfull-scaleinput
A-weighted(1) (2) aSppliedatIN1inputs,0-dBPGAgain 92 dB
f =48kHz,1-kHz–2-dBfull-scaleinputapplied –90 –75 dB
THD Totalharmonicdistortion S
atIN1inputs,0-dBPGAgain 0.003% 0.017%
234Hz,100mV onAVDD,single-endedinput 46
PP
PSRR Powersupplyrejectionratio dB
234Hz,100mV onAVDD,differentialinput 68
PP
ADCchannelseparation 1kHz,–2dBIN1LtoIN1R –73 dB
ADCgainerror 1kHzinput,0-dBPGAgain 0.7 dB
ADCprogrammable-gain
1-kHzinputtone,R <50Ω 40 dB
amplifiermaximumgain SOURCE
ADCprogrammable-gain
0.502 dB
amplifierstepsize
IN1inputs,routedtosingleADC
35
Inputmixattenuation=0dB
Inputresistance IN2inputs,inputmixattenuation=0dB 35 kΩ
IN1inputs,inputmixattenuation=–6dB 62.5
IN2inputs,inputmixattenuation=–6dB 62.5
Inputcapacitance 10 pF
Inputlevelcontrolminimum
0 dB
attenuationsetting
Inputlevelcontrolmaximum
6 dB
attenuationsetting
Inputlevelcontrolattenuation
6 dB
stepsize
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHDandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
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Electrical Characteristics (continued)
At25°C,AVDD=3.3V,IOVDD=1.8V,DVDD=1.8V,f =48-kHz,16-bitaudiodata(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
ADCDIGITALDECIMATIONFILTER f =48kHz
S
Filtergainfrom0to0.39f FilterA,AOSR=128or64 ±0.1 dB
S
Filtergainfrom0.55f to64f FilterA,AOSR=128or64 –73 dB
S S
Filtergroupdelay FilterA,AOSR=128or64 17/f s
S
Filtergainfrom0to0.39f FilterB,AOSR=64 ±0.1 dB
S
Filtergainfrom0.60f to32f FilterB,AOSR=64 –46 dB
S S
Filtergroupdelay FilterB,AOSR=64 11/f s
S
Filtergainfrom0to0.39f FilterC,AOSR=32 ±0.033 dB
S
Filtergainfrom0.28f to16f FilterC,AOSR=32 –60 dB
S S
Filtergroupdelay FilterC,AOSR=32 11/f s
S
MICROPHONEBIAS
2
2.25 2.5 2.75
Biasvoltage Programmablesettings,load=750Ω V
AVDD–
0.2
Currentsourcing 2.5-Vsetting 4 mA
BW=20Hzto20kHz,A-weighted,1-μF μV
Integratednoise 3.3
capacitorbetweenMICBIASandAGND rms
DIGITALI/O
0.3×
V Inputlowlevel I =5μA –0.3 V
IL IL IOVDD
V Inputhighlevel(3) I =5μA 0.7× V
IH IH IOVDD
0.1×
V Outputlowlevel I =2TTLloads V
OL IH IOVDD
0.8×
V Outputhighlevel I =2TTLloads V
OH OH IOVDD
SUPPLYCURRENT f =48kHz,AVDD=3.3V,DVDD=IOVDD=1.8V
S
AVDD 2
Monorecord PLLandAGCoff mA
DVDD 1.9
AVDD 4
Stereorecord PLLandAGCoff mA
DVDD 2.1
AVDD Additionalpowerconsumedwhen 1.1
PLL mA
DVDD PLLispowered 0.8
AVDD Allsupplyvoltagesapplied,allblocks 0.04
Powerdown μA
DVDD programmedinlowestpowerstate 0.7
(3) WhenIOVDD<1.6V,minimumV is1.1V.
IH
8.6 Dissipation Ratings(1)
T =25°C T =75°C T =85°C
PACKAGETYPE A DERATINGFACTOR A A
POWERRATING POWERRATING POWERRATING
VQFN 1.7W 22mW/°C 665mW 444mW
(1) Thisdatawastakenusing2-oz.(0.071-mmthick)traceandcopperpadthatissoldereddirectlytoaJEDECstandard4-layer3-in.×3-
in.(7.62-cm×7.62-cm)PCB.
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8.7 I2S/LJF/RJF Timing in Master Mode
Specifiedat25°C,DVDD=1.8V,alltimingspecificationsaremeasuredatcharacterization.SeeFigure1fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (WS) BCLK/WCLKdelaytime 20 15 ns
d
t (DO-WS) BCLK/WCLKtoDOUTdelaytime 25 20 ns
d
t (DO-BCLK) BCLKtoDOUTdelaytime 20 15 ns
d
t Risetime 20 15 ns
r
t Falltime 20 15 ns
f
8.8 DSP Timing in Master Mode
Specifiedat25°C,DVDD=1.8V,alltimingspecificationsaremeasuredatcharacterization.SeeFigure2fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (WS) BCLK/WCLKdelaytime 25 15 ns
d
t (DO-BCLK) BCLKtoDOUTdelaytime 25 15 ns
d
t Risetime 20 15 ns
r
t Falltime 20 15 ns
f
8.9 I2S/LJF/RJF Timing in Slave Mode
Specifiedat25°C,DVDD=1.8V,alltimingspecificationsaremeasuredatcharacterization.SeeFigure3fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) BCLK/WCLKset-uptime 10 6 ns
s
t (WS) BCLK/WCLKholdtime 10 6 ns
h
BCLK/WCLKtoDOUTdelaytime
t (DO-WS) 30 30 ns
d (forLJFModeonly)
t (DO-BCLK) BCLKtoDOUTdelaytime 25 20 ns
d
t Risetime 16 8 ns
r
t Falltime 16 8 ns
f
8.10 DSP Timing in Slave Mode
Specifiedat25°C,DVDD=1.8V,alltimingspecificationsaremeasuredatcharacterization.SeeFigure4fortimingdiagram.
IOVDD=1.8V IOVDD=3.3V
UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) BCLK/WCLKset-uptime 10 8 ns
s
t (WS) BCLK/WCLKholdtime 10 8 ns
h
t (DO-BCLK) BCLKtoDOUTdelaytime 25 20 ns
d
t Risetime 15 8 ns
r
t Falltime 15 8 ns
f
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WCLK
t(WS)
d
t t
r f
BCLK
t(DO-WS) t(DO-BCLK)
d d
DOUT
Figure1. I2S/LJF/RJFTiminginMasterMode
WCLK
t(WS) t(WS)
d d
t t
f r
BCLK
t(DO-BCLK)
d
DOUT
Figure2. DSPTiminginMaster Mode
WCLK
t (WS)
S
t (WS)
h
t (BCLK)
H
t t
r f
BCLK
t (BCLK) t (DO-WS)
L d
t (DO-BCLK)
d
DOUT
Figure3. I2S/LJF/RJFTiminginSlaveMode
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(see NOTE)
WCLK
th(WS) ts(WS) th(WS) t (WS)
h
BCLK t (BCLK) tL(BCLK)
H
td(DO-BCLK) tf tr
DOUT
NoteA.FallingedgeinsideaframeforWCLKisarbitraryinsideframe.
Figure4. DSPTiminginSlaveMode
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