Low Power Stereo ADC for Wireless Handsets and Portable Audio

88 Pages·2015·1.65 MB·English

TLV320ADC3101
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Low Power Stereo ADC for Wireless Handsets and Portable Audio
FEATURES APPLICATIONS
1
• StereoAudioADC • WirelessHandsets
2
– 92-dBASignal-to-Noise Ratio • PortableLowPowerAudioSystems
– SupportsADCSample RatesFrom8kHzto • NoiseCancellationSystems
96kHz • Front-EndVoiceorAudioProcessor forDigital
• FlexibleDigital FilteringwithRAM Audio
ProgrammableCoefficient,Instructions, and
DESCRIPTION
Built-InStandardModes
– LowLatencyIIRFiltersfor Voice The TLV320ADC3101 is a low power, stereo audio
Analog to Digital Converter (ADC) supporting
– LinearPhaseFIRFiltersforAudio
sampling rates from 8 kHz to 96 kHz with an
– AdditionalProgrammableIIRFiltersforEQ, integrated programmable gain amplifier providing up
NoiseCancellationorReduction to 40dB analog gain or AGC. Front-end input coarse
– Up to128ProgrammableADCDigitalFilter attenuation of 0dB, –6dB, or off, is also provided. The
inputs are programmable in a combination of
Coefficients
single-ended or fully differential configurations.
• SixAudioInputsWithConfigurableAutomatic
Extensive register-based power control is available
GainControl(AGC) via I2C, enabling mono or stereo recording. Low
– ProgrammableinSingle-Ended or Fully power consumption makes the TLV320ADC3101
DifferentialConfigurations idealfor battery-poweredportableequipment.
– Canbe3-Statedfor EasyInteroperability The AGC programs to a wide range of attack
WithOther AudioICs (7ms – 1.4s) and decay (50ms – 22.4s) times. A
• LowPowerConsumptionand Extensive programmable noise gate function is included to
avoidnoisepumping.Low-latencyIIR filters optimized
ModularPower Control:
for voice and telephony are available, as well as
– 6-mW MonoRecord8-kHz
linear-phase FIR filters optimized for audio.
– 11-mWStereoRecord,8-kHz Programmable IIR filters are also available and may
be used for sound equalization, or to remove noise
– 10-mWMono Record,48-kHz
components. The audio serial bus can be
– 17-mWStereoRecord,48-kHz programmed to support I2S, Left-justified,
• DualProgrammableMicrophoneBias Right-justified, DSP, PCM, and TDM modes. The
• ProgrammablePLLfor ClockGeneration audio bus may be operated in either master or slave
mode.
• I2C™ControlBus
• AudioSerialDataBusSupports I2S, A programmable integrated PLL is included for
flexible clock generation and support for all standard
Left/Right-Justified,DSP,PCM,andTDM
audio rates from a wide range of available MCLKs,
Modes
varying from 512 kHz to 50 MHz, including the most
• DigitalMicrophoneInputSupport popular cases of 12-MHz, 13-MHz, 16-MHz,
• TwoGPIOs 19.2-MHz, and19.68-MHzsystem clocks.
• PowerSupplies:
– Analog: 2.6V–3.6V.
– Digital:Core:1.65V–1.95V,
I/O:1.1V–3.6V
• 4mm×4mm24-PinRGE (QFN)
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
I2CisatrademarkofPhillipsElectronics.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2008,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
TLV320ADC3101
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Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
SIMPLIFIED BLOCK DIAGRAMS
1 0
R R
D D
DOUT BCLK WCLK 2C_A 2C_A
I I
E
G SDA
C3101ROption 2ISTDMSerialBusInterface 2ICSerialControl Bus SCL
D
AN RESET
0F
2Q
3
V
L
CLK/GPIO2 T Effects/Filtering Effects/Filtering Audio ClockGenerationPLL MCLK
M
D
nee DINL
DigitalMicrophoInterfac DINR MicBias2 MICBIAS2
1
O
PI
G C C
N/ D D 1
DI A A Micas MICBIAS1
M Bi
D
B B
AGC PGA0/+59.5d0.5 dBSteps AGC PGA0/+59.5d0.5 dBSteps urrent Bias/Reference IDDAOVVVVSSDDSSDD
C
AVDD
AnalogSignal InputcShiwintgandAttenuation
P) P) M) M) P) M)
IN1L( IN2L( IN3L( IN1R( IN2R( IN3R(
Figure1.TLV320ADC3101RGEBlockDiagram
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PACKAGING/ORDERINGINFORMATION
OPERATING
PRODUCT PACKAGE(1) PACKAGE TEMPERATURE ORDERING TRANSPORT
DESIGNATOR NUMBER MEDIA,QUANTITY
RANGE
TLV320ADC3101IRGET TapeandReel250
TLV320ADC3101 QFN-24 RGE –40°Cto85°C
TLV320ADC3101IRGER TapeandReel2500
(1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
PIN ASSIGNMENTS
TLV320ADC3101
RGEPACKAGE
(TOPVIEW)
O2 O1
PI PI
G G
D K/ N/
CLK VSS VDD OD MCL MDI
M D D V D D
I
4 3 2 1 0 9
2 2 2 2 2 1
BCLK 1 18 SDA
WCLK 2 17 SCL
2
DOUT 3 16 I C_ADR1
2
RESET 4 15 I C_ADR0
MICBIAS1 5 14 MICBIAS2
IN3L(M) 6 13 IN3R(M)
7 8 9 10 11 12
L(P) L(P) VSS VDD R(M) R(P)
N2 N1 A A N1 N2
I I I I
ConnecttheQFNthermalpadtoAVSS.
PINFUNCTIONS
TLV320ADC3101RGE
PINNAME DESCRIPTION
QFN
1 BCLK AudioSerialDataBusBitClock(Input/Output)
2 WCLK AudioSerialDataBusWordClock(Input/Output)
3 DOUT AudioSerialDataBusDataOutput(Output)
4 RESET Reset
5 MICBIAS1 Microphonebiasvoltageoutput
6 IN3L(M) MicorLineAnalogInput(LeftchannelS.E.orD.EMinus)
7 IN2L(P) MicorLineAnalogInput(LeftchannelS.E.orD.EPlus)
8 IN1L(P) MicorLineAnalogInput(LeftchannelS.E.orD.EPlus,orRightchannel)
9 AVSS AnalogGroundSupply,0V
10 AVDD AnalogVoltageSupply,2.6V-3.6V
11 IN1R(M) MicorLineAnalogInput(LeftchannelS.E.orD.EMinus,orLeftchannel)
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PINFUNCTIONS(continued)
TLV320ADC3101RGE
PINNAME DESCRIPTION
QFN
12 IN2R(P) MicorLineAnalogInput(RightchannelS.E.orD.EPlus)
13 IN3R(M) MicorLineAnalogInput(RightchannelS.E.orD.EMinus)
14 MICBIAS2 Microphonebiasvoltageoutput
15 I2C_ADR0 LSBofI2CBusaddress
16 I2C_ADR1 LSB+1ofI2CBusaddress
17 SCL I2CSerialClock
18 SDA I2CSerialDataInput/Output
DigitalMicrophoneDataInput/General-PurposeInput/Output#1(Input/Output)/PLLClock
19 DMDIN/GPIO1
MuxOutput/AGCNoiseFlag/Multi-functionpinbasedonregisterprogramming
DigitalMicrophoneClock/General-PurposeInput/Output#2(Input/Output)/PLLClockInput/
20 DMCLK/GPIO2
AudioSerialDataBusBitClockInput/Output/Multi-functionpinbasedonregisterprogramming
21 IOVDD I/OVoltageSupply,1.1V–3.6V
22 DVDD DigitalCoreVoltageSupply,1.65V–1.95V
23 DVSS DigitalGroundSupply,0V
24 MCLK MasterClockInput
ABSOLUTE MAXIMUM RATINGS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) (2)
VALUE UNIT
AVDDtoAVSS –0.3to3.9 V
IOVDDtoDVSS –0.3to3.9 V
DVDDtoDVSS –0.3to2.5 V
DigitalinputvoltagetoDVSS –0.3VtoIOVDD+0.3 V
AnaloginputvoltagetoAVSS –0.3VtoAVDD+0.3 V
Operatingtemperaturerange -40to85 °C
Storagetemperaturerange –65to125 °C
T Max Junctiontemperature 105 °C
J
Powerdissipation (T Max–T )/q
J A JA
q Thermalimpedance,QFNpackage 45 °C/W
JA
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
(2) ESDcomplacencetestedtoEIA/JESD22-A114-Bandpassed.
DISSIPATION RATINGS(1)
T =25°C T =75°C T =85°C
PACKAGETYPE A DERATINGFACTOR A A
POWERRATING POWERRATING POWERRATING
QFN 1.7W 22mW/°C 665mW 444mW
(1) Thisdatawastakenusing2oz.traceandcopperpadthatissoldereddirectlytoaJEDECstandard4-layer3in×3inPCB.
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RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) Analogsupplyvoltage 2.6 3.3 3.6 V
DVDD(1) Digitalcoresupplyvoltage 1.65 1.8 1.95 V
IOVDD(1) DigitalI/Osupplyvoltage 1.1 1.8 3.6 V
V Analogfull-scale0dBinputvoltage(AVDD=3.3V) 0.707 Vrms
I
Digitaloutputloadcapacitance 10 pF
T Operatingfree-airtemperature –40 85 °C
A
(1) AnalogvoltagevaluesarewithrespecttoAVSS;digitalvoltagevaluesarewithrespecttoDVSS.
ELECTRICAL CHARACTERISTICS
At25°C,AVDD,IOVDD=1.8V,DVDD=1.8V,Fs=48-kHz,16-bitaudiodata(unlessotherwisenoted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
AUDIOADC
Inputsignallevel(0-dB) Single-endedinput 0.707 Vrms
Signal-to-noiseratio, Fs=48kHz,0dBPGAgain,IN1inputsselected
80 92 dB
A-weighted(1) (2) andAC-shortedtoground
Dynamicrange, Fs=48kHz,1-kHz–60dBfull-scaleinput
A-weighted(1) (2) appliedatIN1inputs,0-dBPGAgain 92 dB
Fs=48kHz,1-kHz–2dBfull-scaleinputapplied –90 –75 dB
THD Totalharmonicdistortion atIN1
inputs,0-dBPGAgain 0.003% 0.017%
234Hz,100mV onAVDD,single-endedinput 46
PP
Powersupplyrejectionratio dB
234Hz,100mV onAVDD,differentialinput 68
PP
ADCchannelseparation 1kHz,–2dBIN1LtoIN1R –73 dB
ADCgainerror 1kHzinput,0dBPGAgain 0.7 dB
ADCprogrammablegainamplifier
1-kHzinputtone,R <50Ω 40 dB
maximumgain SOURCE
ADCprogrammablegainamplifier
0.502 dB
stepsize
IN1inputs,routedtosingleADC
35
Inputmixattenuation=0dB
Inputresistance IN2inputs,inputmixattenuation=0dB 35 kΩ
IN1inputs,inputmixattenuation=–6dB 62.5
IN2inputs,inputmixattenuation=–6dB 62.5
Inputcapacitance 10 pF
Inputlevelcontrolminimum
0 dB
attenuationsetting
Inputlevelcontrolmaximum
6 dB
attenuationsetting
Inputlevelcontrolattenuationstep
6 dB
size
(1) Ratioofoutputlevelwith1-kHzfull-scalesinewaveinput,totheoutputlevelwiththeinputsshortcircuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
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ELECTRICAL CHARACTERISTICS (continued)
At25°C,AVDD,IOVDD=1.8V,DVDD=1.8V,Fs=48-kHz,16-bitaudiodata(unlessotherwisenoted)
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
ADCDIGITALDECIMATIONFILTER Fs=48kHz
Filtergainfrom0to0.39Fs FilterA,AOSR=128or64 ±0.1 dB
Filtergainfrom0.55Fsto64Fs FilterA,AOSR=128or64 -73 dB
Filtergroupdelay FilterA,AOSR=128or64 17/Fs Sec
Filtergainfrom0to0.39Fs FilterB,AOSR=64 ±0.1 dB
Filtergainfrom0.60Fsto32Fs FilterB,AOSR=64 -46 dB
Filtergroupdelay FilterB,AOSR=64 11/fs Sec
Filtergainfrom0to0.39Fs FilterC,AOSR=32 ±0.033 dB
Filtergainfrom0.28Fsto16Fs FilterC,AOSR=32 -60 dB
Filtergroupdelay FilterC,AOSR=32 11/fs Sec
MICROPHONEBIAS
2
Biasvoltage Programmablesettings,load=750Ω 2.25 2.5 2.75 V
AVDD-0.2
Currentsourcing 2.5Vsetting 4 mA
DIGITALI/O
V Inputlowlevel I =5m A –0.3 0.3× V
IL IL IOVDD
V Inputhighlevel(3) I =5m A 0.7× V
IH IH IOVDD
0.1×
V Outputlowlevel I =2TTLloads V
OL IH IOVDD
0.8×
V Outputhighlevel I =2TTLloads V
OH OH IOVDD
SUPPLYCURRENT Fs=48-kHz,AVDD=3.3V,DVDD=IOVDD=1.8V
AVDD 2
Monorecord PLLandAGCoff mA
DVDD 1.9
AVDD 4
Stereorecord PLLandAGCoff mA
DVDD 2.1
AVDD Additionalpowerconsumedwhen 1.1
PLL mA
DVDD PLLispowered 0.8
Powerdown AVDD Allsupplyvoltagesapplied,allblocks 0.04 m A
DVDD programmedinlowestpowerstate 0.7
(3) WhenIOVDD<1.6V,minimumV is1.1V.
IH
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AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS
Allspecificationsat25°C,DVDD=1.8V
WCLK
t (WS)
d
BCLK
t (DO-WS) t (DO-BCLK)
d d
DOUT
IOVDD=1.8V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (WS) BCLK/WCLKdelaytime 20 15 ns
d
t (DO-WS) BCLK/WCLKtoDOUTdelaytime 25 20 ns
d
t (DO-BCLK) BCLKtoDOUTdelaytime 20 15 ns
d
t Risetime 20 15 ns
r
t Falltime 20 15 ns
f
NOTE: Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest.
Figure2.I2S/LJF/RJFTiminginMaster Mode
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Allspecificationsat25°C,DVDD=1.8V
WCLK
t (WS) t (WS)
d d
BCLK
t (DO-BCLK)
d
DOUT
IOVDD=1.8V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (WS) BCLK/WCLKdelaytime 25 15 ns
d
t (DO-BCLK) BCLKtoDOUTdelaytime 25 15 ns
d
t Risetime 20 15 ns
r
t Falltime 20 15 ns
f
NOTE: Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest.
Figure3. DSPTiminginMaster Mode
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Allspecificationsat25°C,DVDD=1.8V
WCLK
t (WS)
S
t (WS)
h
t (BCLK)
H
BCLK
t (BCLK) t (DO-WS)
L d
t (DO-BCLK)
d
DOUT
IOVDD=1.8V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) BCLK/WCLKsetuptime 10 6 ns
s
t (WS) BCLK/WCLKholdtime 10 6 ns
h
t (DO-WS) BCLK/WCLKtoDOUTdelaytime(forLJFModeonly) 30 30 ns
d
t (DO-BCLK) BCLKtoDOUTdelaytime 25 20 ns
d
t Risetime 16 8 ns
r
t Falltime 16 8 ns
f
NOTE: Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest.
Figure4.I2S/LJF/RJFTimingin SlaveMode
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Allspecificationsat25°C,DVDD=1.8V
WCLK
t (WS)
S
t (WS)
h
t (BCLK)
H
BCLK
t (BCLK) t (DO-WS)
L d
t (DO-BCLK)
d
DOUT
IOVDD=1.8V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) BCLK/WCLKsetuptime 10 8 ns
s
t (WS) BCLK/WCLKholdtime 10 8 ns
h
t (DO-BCLK) BCLKtoDOUTdelaytime 25 20 ns
d
t Risetime 15 8 ns
r
t Falltime 15 8 ns
f
NOTE: Alltimingspecificationsaremeasuredatcharacterizationbutnottestedatfinaltest.
Figure5.DSPTiminginSlaveMode
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