Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction

164 Pages·2004·6.59 MB·English

by  P. R. van der Meer, A. van Staveren, A. H. M. van Roermund (auth.)

LOW-POWER DEEP SUB-MICRON CMOS LOGIC
THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND
COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor: Mohammed Ismail. Ohio State University
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LOW-POWER DEEP
SUB-MICRON CMOS LOGIC
Sub-threshold Current Reduction
By
P.R. van der Meer
Delft University of Technology,
Delft, The Netherlands
and
A. van Staveren
National Semiconductor Corporation,
Delft, The Netherlands
and
A.H.M. van Roermund
Eindhoven University of Technology,
Eindhoven, The Netherlands
KLUWER ACADEMIC PUBLISHERS
BOSTON I DORDRECHT I LONDON
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4757-1057-1 ISBN 978-1-4020-2849-6 (eBook)
DOI 10.1007/978-1-4020-2849-6
Published by Kluwer Academic Publishers,
P.O. Box 17, 3300 AA Dordrecht, The Netherlands.
Sold and distributed in North, Central and South America
by Kluwer Academic Publishers,
\01 Philip Drive, Norwell, MA 02061, U.S.A.
In all other countries, sold and distributed
by Kluwer Academic Publishers,
P.O. Box 322, 3300 AH Dordrecht, The Netherlands.
Printed on acid-free paper
All Rights Reserved
© 2004 Kluwer Academic Publishers, Boston
Softcover reprint of the hardcover 1s t edition 2004
No part of this work may be reproduced, stored in a retrieval system, or transmitted
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Contents
Index of symbols IX
1. INTRODUCTION 1
1.1 Power-dissipation trends in CMOS circuits 1
1.2 Overview of present power-reduction solutions 2
1.3 Aim and scope of this book 3
1.4 Organization of the book 4
2. POWER VERSUS ENERGY 5
2.1 Power considerations 5
2.2 Energy considerations 8
2.3 Conclusions 9
3. POWER DISSIPATION IN DIGITAL CMOS CIRCUITS 11
3.1 Thermodynamics of computation 13
3.1.1 Fundamental limits of power dissipation 14
3.1.2 Thermodynamic laws 17
3.2 Functional power dissipation 19
3.3 Parasitical power dissipation 22
3.3.1 Leakage power dissipation 24
3.3.1.1 Channel leakage current 24
3.3.1.2 Diode leakage current 38
3.3.1.3 Gate leakage current 42
3.3.2 Short-circuit power dissipation 45
3.4 Trends in power dissipation 48
3.5 Conclusions 49
v
vi CONTENTS
4. REDUCTION OF FUNCTIONAL POWER DISSIPATION 53
4.1 Node transition-cycle activity factor 53
4.2 Clock frequency 54
4.3 Transition-cycle energy 54
4.3.1 Reversibility factor 57
4.3.1.1 Ramp-wise charging 59
4.3.1.2 Step-wise charging 61
4.3.1.3 Resonant charging 63
4.3.2 Load capacitance 68
4.3.3 Voltage swing 69
4.3.3.1 Static voltage scaling 70
4.3.3.2 Dynamic voltage scaling 72
4.4 Conclusions 75
5. REDUCTION OF PARASITICAL POWER DISSIPATION 77
5.1 Leakage power dissipation 77
5.1.1 Channel leakage current 78
5.1.1.1 Weak-inversion current 78
5.1.1.2 Drain-Induced Barrier Lowering current 80
5.1.1.3 Channel edge current 81
5.1.2 Diode leakage current 83
5.1.2.1 Reverse bias leakage 83
5.1.2.2 Gate-induced drain leakage 84
5.1.3 Gate leakage current 85
5.2 Short-circuit power dissipation 89
5.3 Need for weak-inversion current reduction 90
5.4 Conclusions 91
6. WEAK-INVERSION CURRENT REDUCTION 93
6.1 Classification 93
6.1.1 Power reduction with state retention 94
6.1.1.1 Storage in intrinsically low-leakage memory 95
6.1.1.2 Substrate biasing 96
6.1.1.3 Source and gate biasing 97
6.1.1.4 Fixed high threshold voltage 99
6.1.1.5 Triple-S Technique 100
6.1.2 Power reduction without state retention 102
6.2 Conclusions 104
vii
7. EFFECTIVENESS OF WEAK-INVERSION CURRENT
REDUCTION 105
7.1 General effectiveness 105
7.1.1 Ideal case 106
7.1.2 Dissipation of stored energy 107
7.1.3 Overhead costs 108
7.2 Technique-specific effectiveness 111
7.2.1 Effectiveness of substrate biasing 111
7.2.2 Effectiveness of source and gate biasing 113
7.2.3 Effectiveness of the Trip1e-S technique 117
7.3 Conclusions 120
8. TRIPLE-S CIRCUIT DESIGNS 121
8.1 Process flow 121
8.2 Experimental circuits 123
8.3 Leakage, speed, area and functional power 125
8.3.1 Leakage 126
8.3.2 Speed 129
8.3.3 Area 131
8.3.4 Functional power 132
8.4 Practical applications and limitations 135
8.5 Conclusions 137
9. CONCLUSIONS 139
10. SUMMARY 141
References 145
Index
151
Index of symbols
Symbol Meaning Unit
a Node transition-cycle activity factor
aij Node transition-cycle activity factor a of
node j in clock period i
(3 Effective transistor strength A. V- 2
'Y Body factor V-~
8 Relative increase of the logic gate capaci-
tance
E Unit step function
7] Reversibility factor
() Phase angle between voltage and current radians
0
()t STI transition angle
{} DIBL factor
K, Inverse scaling factor
f.Lo Zero bias mobility m 2 • V-1s-1
f.Ln Electron mobility m 2 • V-1s-1
f.Lp Hole mobility m 2 . V-1s-1
v Carrier mobility temperature exponent
(J" Drain-source saturation current exponent
T Characteristic time; product of Rand C s
Td Time delay s
Tj Fall time s
Tl Carrier lifetime s
Tpd Propagation delay s
Tr Rise time s
c/>p Fermi potential V
c/>gc Gate-channel work-function difference V
X Threshold voltage temperature coefficient V·K- 1
ix
x
1/Js Surface potential
Wo Oscillation frequency
Q Diminutive
eCT Instantaneous energy of the tank capacitance
iclk Clock frequency
h Isolation height with respect to the silicon
surface
iCL Instantaneous current through the load A
(node) capacitance
Zsc Instantaneous short -circuit current
k Boltzmann's constant, 1.380658 . 10-23
n Slope factor
na Number of atoms
ni Intrinsic concentration of electrons
npO Thermal-equilibrium concentration of mi-
nority electrons in a p-type region
P Number of voltage steps in the step-wise
charging technique
Pdn,ij Instantaneous power delivered to the power w
supply to discharge node j in clock period i
Pij Instantaneous power delivered by or to the w
power supply to charge or discharge node j
in clock period i
PnO Thermal-equilibrium concentration of mi-
nority holes in an n-type region
Pup,ij Instantaneous power delivered by the power w
supply to charge node j in clock period i
q Electron charge, 1.602177. 10-19 c
r STI comer radius m
Sw Wire spacing m
tdep Depletion region thickness m
ti Clock period i S
tj Junction depth m
tox Gate oxide thickness m
tw Wire thickness m
UCL Instantaneous voltage across the load (node) V
capacitance
Instantaneous voltage across a resistor
Instantaneous logic voltage swing
Gate area
Source-bulk or drain-bulk pn-junction area
Wiring area
xi
C Capacitance F
Cclk_std Switched capacitance of the clock circuitry F
of a standard circuit
Cclk_TS Switched capacitance of the clock circuitry F
of a Triple-S circuit
C' Depletion capacitance per unit area F ·m- 2
d
Cdata_std Switched capacitance of a standard circuit, F
when all data bits change state every clock
cycle
Cdata_TS Switched capacitance of a Triple-S circuit, F
when all data bits change state every clock
cycle
C g Gate capacitance F
C· Junction capacitance F
J
CL Load (node) capacitance F
Cnode Circuit node capacitance F
Cox Gate oxide capacitance F
C~x Gate oxide capacitance per unit area F ·m- 2
Cpad Bond-pad capacitance F
Cs Series capacitance F
CT Tank capacitance F
C~h Heat capacitance per unit area ]. K-1. m-2
C w Wiring capacitance F
Dn Electron diffusion coefficient m 2 ·8-1
Dp Hole diffusion coefficient m 2 ·8-1
Ebattery Energy stored in a battery A·hor]
Ec Conduction band energy (top edge) ] oreV
ECL Energy stored in the load capacitor ]
Ecycle Transition-cycle energy ]
Edn Energy delivered to the power supply to dis- ]
charge a circuit node
Edn,ij Energy delivered to the power supply to dis- ]
charge node j in clock period i
Ep Fenni energy ] oreV
Epi Intrinsic Fenni energy ] oreV
Ejunc Functional energy ]
Eg Band gap energy ] oreV
Ei Initial energy ]
Eins Electric field in the gate insulator V·m- 1
Eint Internal energy of a process ]
Eoverhead Excess energy consumption ]
Eox Electric field in the gate oxide V ·m-1