Low-Power Audio Codec With Embedded miniDSP and Stereo Class-D Speaker Amplifier

157 Pages·2016·1.74 MB·English

TLV320AIC3111
www.ti.com SLAS644D–JULY2009–REVISEDMAY2012
Low-Power Audio Codec With Embedded miniDSP
and Stereo Class-D Speaker Amplifier
CheckforSamples:TLV320AIC3111
1 INTRODUCTION
1.1 Features 1.2 Applications
• StereoAudioDACWith95-dBSNR • PortableAudioDevices
1234
• MonoAudioADCWith91-dBSNR • MobileInternet Devices
• Supports8-kHzto192-kHzSeparateDACand
• AdaptiveFilteringApplications
ADCSampleRates
• Instruction-ProgrammableEmbeddedminiDSP
1.3 Description
• Stereo 1.29-WClass-DBTL8-ΩSpeakerDriver
WithDirectBatteryConnection The TLV320AIC3111 is a low-power, highly
• OneDifferentialand ThreeSingle-Ended Inputs integrated, high-performance codec which provides a
WithMixingandLevelControl stereoaudioDACandmonoaudioADC.
• MicrophoneWith Bias,PreampPGA,andAGC
The TLV320AIC3111 features a high-performance
• Built-inDigitalAudioProcessingBlocksWith
audio codec with 16-bit stereo playback and
User-ProgrammableBiquadand FIRFilters
monaural record functionality. The device integrates
• DigitalMixingCapability
several analog features, such as a microphone
• ProgrammableDigitalAudioProcessorfor
interface,headphonedrivers, andspeakerdrivers.
BassBoost/Treble/EQWithuptoFiveBiquads
forRecordanduptoSixBiquadsforPlayback The TLV320AIC3111 has a fully programmable
• PinControlor RegisterControl forDigital- miniDSP for digital audio processing. The digital
PlaybackVolume-Control Settings audio data format is programmable to work with
• Sine-WaveGeneratorfor Beep popular audio standard protocols (I2S, left-/ right-
• IntegratedPLLUsedforProgrammableDigital justified) in master, slave, DSP, and TDM modes.
AudioProcessor Bass boost, treble, or EQ can be supported by the
• I2S,Left-Justified, Right-Justified,DSP,and programmabledigitalsignal-processingblock.
TDMAudioInterfaces
An on-chip PLL provides the high-speed clock
• I2CControlWith RegisterAuto-Increment
needed by the digital signal processing block. The
• FullPower-Down Control
volume level can be controlled by either pin control or
• PowerSupplies:
by register control. The audio functions are controlled
– Analog:2.7V–3.6V usingtheI2Cserialbus.
– DigitalCore:1.65V–1.95V
The TLV320AIC3111 has a programmable beep
– DigitalI/O:1.1V–3.6V
generatorandisavailableina32-pinQFNpackage.
– Class-D: 2.7V–5.5V(SPLVDD and
SPRVDD≥ AVDD)
• 5-mm× 5-mm32-QFNPackage
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PurePathisatrademarkofTexasInstruments.
2
MATLABisatrademarkofTheMathWorks,Inc.
3
Allothertrademarksarethepropertyoftheirrespectiveowners.
4
PRODUCTIONDATAinformationiscurrentasofpublicationdate.Productsconformto Copyright©2009–2012,TexasInstrumentsIncorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processingdoesnotnecessarilyincludetestingofallparameters.
TLV320AIC3111
SLAS644D–JULY2009–REVISEDMAY2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
SPLVDD SPRVDD SPLVSS SPRVSS HPVDD HPVSS AVDD AVSS
2 V/2.5 V/AVDD
MICBIAS
P1/R33–R34 De-Pop
VOL/ 7-Bit and Audio Output Stage
MICDET AVDoCl SSotaftr-t Power Management
Left and Right Volume-
Control Register RC CLK
P0/R116–R117
Class-D Speaker AnalogAttenuation
Driver 0 dB to–78 dB and Mute GPIO GPIO1
(0.5-dB Steps / Nonlinear)
SPLP P1/R42 P1/R38 MIX_L
SPLM
6 dB to 24 dB (6-dB Steps)
SPRP P1/R32 P1/R43 P1/R39 MIX_R I2C SSCDLA
SPRM
P1/R30
ClassA/B AnalogAttenuation
Headphone/Lineout 0 dB to–78 dB and Mute
Driver (0.5-dB Steps / Nonlinear)
P1/R40 P1/R36 MIX_L
HPL
P1/R31 0 dB to 9 dB (1-dB Steps) Note: Normally,
MCLK is PLLinput;
P1/R44 P1/R41 P1/R37 MIX_R however, BCLK,
HPR GPIO1, etc., can
also be PLLinput.
MIX_R
MIX_L PLL MCLK
MIC1LP
S DAC_L D-S S S
DAC
MIC1RP Digital Vol
P1/R35 24 dB to miniDSP P0/R63
Mute Digital
Audio
S DAC_R D-S S S Processing
DAC P0/ and
R64–R65 Serial
Digital P0/R71 Digital Beep Interface DOUT
P0/R72
Vol Ctl Generator WCLK
0 to–63 dB
(1-dB Steps) DIN
P1/R47
0 to 59.5 dB BCLK
MIC1LP (0.5-dB steps) MonoADC P0/R82–R83
S D-S Digital Vol
ADC –12..20 dB miniDSP RESET
MIC1RP Step = 0.5 dB
P1/R48
Selectable P0/R86–R93
Gain/Input
Impedance AGC
S
MIC1LM
OSC
VCOM
Input CM Selectable P1/R49 RC CLK
P1/R50 Gain/Input
Impedance
DVDD DVSS IOVDD IOVSS
B0205-05
Figure1-1. Functional BlockDiagram
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NOTE
Thisdatamanualis designedusingPDFdocument-viewingfeatures thatallowquick access
to information. For example, performing a global search on "page 0 / register 27" produces
all references to this page and register in a list. This makes it easy to traverse the list and
find allinformationrelatedto apage andregister. Note thatthesearch string mustbe of the
indicated format. Also, this document includes document hyperlinks to allow the user to find
a document reference quickly. To come back to the original page, click the green left arrow
near the PDF page number at the bottom of the file. The hot-key for this function is alt-left
arrowonthekeyboard.AnotherwaytofindinformationquicklyistousethePDFbookmarks.
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2 PACKAGE AND SIGNAL DESCRIPTIONS
2.1 Package/Ordering Information
See the Package Option Addendum at the end of this data manual for information regarding the device
packageandorderingofparts.
2.2 Device Information
RHB Package
(Top View)
D D S
VD M P VD VS M S D
R R L L L L S D
P P P P P P V V
S S S S S S D A
24 23 22 21 20 19 18 17
SPRVSS 25 16 AVSS
SPRP 26 15 MIC1LM
HPL 27 14 MIC1RP
HPVDD 28 13 MIC1LP
TLV320AIC3111
HPVSS 29 12 MICBIAS
HPR 30 11 VOL/MICDET
RESET 31 10 SCL
GPIO1 32 9 SDA
1 2 3 4 5 6 7 8
S D D T N K K K
VS VD VD OU DI CL CL CL
O O D D W B M
I I
P0048-09
Table2-1. TERMINALFUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AVDD 17 – Analogpowersupply
AVSS 16 – Analogground
BCLK 7 I/O Audioserialbitclock
DIN 5 I Audioserialdatainput
DOUT 4 O Audioserialdataoutput
DVDD 3 – Digitalpower–digitalcore
DVSS 18 – Digitalground
GPIO1 32 I/O General-purposeinput/outputandmultifunctionpin
HPL 27 O Left-channelheadphone/linedriveroutput
HPR 30 O Right-channelheadphone/linedriveroutput
HPVDD 28 – Headphone/linedriverandPLLpower
HPVSS 29 – Headphone/linedriverandPLLground
IOVDD 2 – Interfacepower
IOVSS 1 – Interfaceground
MCLK 8 I Exterrnalmasterclock
MICBIAS 12 O Micophonebiasvoltage
MIC1LM 15 I Microphone/lineinputroutedtoMorPinputmixer
MIC1LP 13 I Microphone/lineinputroutedtoPinputmixerandleftoutputmixer
MIC1RP 14 I Microphone/lineinputroutedtoPinputmixerandleft/rightoutputmixer
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Table2-1.TERMINALFUNCTIONS(continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
RESET 31 I Devicereset
SCL 10 I/O I2Ccontrolbusclockinput
SDA 9 I/O I2Ccontrolbusdatainput
SPLM 19 O Left-channelclass-Dspeakerdriverinvertingoutput
SPLP 22 O Left-channelclass-Dspeakerdrivernoninvertingoutput
SPLVDD 21 – Left-channelclass-Dspeakerdriverpowersupply
SPLVSS 20 – Left-channelclass-Dspeakerdriverpowersupplyground
SPRM 23 O Right-channelclass-Dspeakerdriverinvertingoutput
SPRP 26 O Right-channelclass-Dspeakerdrivernoninvertingoutput
SPRVDD 24 – Right-channelclass-Dspeakerdriverpowersupply
SPRVSS 25 – Right-channelclass-Dspeakerdriverpowersupplyground
VOL/MICDET 11 I Volumecontrolormicrophonedetection
WCLK 6 I/O Audioserialwordclock
3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)
VALUE UNIT
AVDDtoAVSS –0.3to3.9 V
DVDDtoDVSS –0.3to2.5 V
HPVDDtoHPVSS –0.3to3.9 V
SPLVDDtoSPLVSS –0.3to6 V
SPRVDDtoSPRVSS –0.3to6 V
IOVDDtoIOVSS –0.3to3.9 V
Digitalinputvoltage IOVSS–0.3toIOVDD+0.3 V
Analoginputvoltage AVSS–0.3toAVDD+0.3 V
Operatingtemperaturerange –40to85 °C
Storagetemperaturerange –55to150 °C
Junctiontemperature(T Max) 105 °C
J
Powerdissipation (T Max–T )/R W
J A θJA
QFNpackage
R thermalimpedance(withthermalpadsolderedtoboard) 35 °C/W
θJA
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
3.2 THERMAL CHARACTERISTICS
Thisdatawastakenusing2-oz.(0.071-mmthick)traceandcopperpadthatissolderedtoaJEDEChigh-K,standard4-layer
3-in.×3-in.(7.62-cm×7.62-cm)PCB.
PowerRatingat25°C DeratingFactor PowerRatingat70°C PowerRatingat85°C
2.3W 28.57mW/°C 1W 0.6W
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3.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) ReferencedtoAVSS(2) 2.7 3.3 3.6
DVDD ReferencedtoDVSS(2) 1.65 1.8 1.95
HPVDD ReferencedtoHPVSS(2) 2.7 3.3 3.6 V
Power-supplyvoltagerange
SPLVDD(1) ReferencedtoSPLVSS(2) 2.7 5.5
SPRVDD(1) ReferencedtoSPRVSS(2) 2.7 5.5
IOVDD ReferencedtoIOVSS(2) 1.1 3.3 3.6
Resistanceappliedacrossclass-Doutputpins
Speakerimpedance 8 Ω
(BTL)
Headphoneimpedance AC-coupledtoR 16 Ω
L
Analogaudiofull-scaleinput
V AVDD=3.3V,single-ended 0.707 V
I voltage RMS
Stereolineoutputload
ACcoupledtoR 10 kΩ
impedance L
MCLK(3) Masterclockfrequency IOVDD=3.3V 50 MHz
f SCLclockfrequency 400 kHz
SCL
T Operatingfree-airtemperature –40 85 °C
A
(1) Tominimizebattery-currentleakage,theSPLVDDandSPRVDDvoltagelevelsshouldnotbebelowtheAVDDvoltagelevel.
(2) Allgroundsonboardaretiedtogether,sotheyshouldnotdifferinvoltagebymorethan0.2Vmaximumforanycombinationofground
signals.Byuseofawidetraceorgroundplane,ensurealow-impedanceconnectionbetweenHPVSSandDVSS.
(3) Themaximuminputfrequencyshouldbe50MHzforanydigitalpinusedasageneral-purposeclock.
3.4 Electrical Characteristics
At25°C;AVDD,HPVDD,IOVDD=3.3V;SPLVDD,SPRVDD=3.6V;DVDD=1.8V;f (audio)=48kHz;
S
CODEC_CLKIN=256×f ;PLL=Off;VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
INTERNALOSCILLATOR—RC_CLK
Oscillatorfrequency 8.2 MHz
VOLUMECONTROLPIN(ADC);VOL/MICDETPINENABLED
VOL/MICDETpinconfiguredasvolumecontrol(page0/ 0.5×
Inputvoltagerange 0 V
register116,bitD7=1andpage0/register67,bitD7=0) AVDD
Inputcapacitance 2 pF
Volumecontrolsteps 128 Steps
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ElectricalCharacteristics(continued)
At25°C;AVDD,HPVDD,IOVDD=3.3V;SPLVDD,SPRVDD=3.6V;DVDD=1.8V;f (audio)=48kHz;
S
CODEC_CLKIN=256×f ;PLL=Off;VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
AUDIOADC
MicrophoneInputtoADC,984-HzSine-WaveInput,f =48kHz,AGC=OFF
S
MICwithR1=20kΩ(page1/register48andpage1/
Inputsignallevel(0-dB) 0.707 V
register49,bitsD7–D6) RMS
f =48kHz,0-dBPGAgain,MICinputac-shortedto
S
SNR Signal-to-noiseratio ground;measuredasidle-channelnoise, 80 91 dB
A-weighted(1) (2)
f =48kHz,0-dBPGAgain,MICinput1kHzat–60-dBFS
S
Dynamicrange inputapplied,referencedto0.707-Vrmsinput,A-weighted(1) 91 dB
(2)
Totalharmonicdistortion+ f =48kHz,0-dBPGAgain,MICinput1kHzat–2dBFS
THD+N S –85 –70 dB
noise inputapplied,referencedto0.707Vrmsinput
f =48kHz,0-dBPGAgain,MICinput1kHzat–2dBFS
THD Totalharmonicdistortion S –91 dB
inputapplied,referencedto0.707Vrmsinput
Inputcapacitance MICinput 2 pF
MicrophoneBias
Page1/register46,bitsD1–D0=10 2.25 2.5 2.75
Voltageoutput V
Page1/register46,bitsD1–D0=01 2
At4-mAloadcurrent,page1/register46,
5
bitsD1–D0=10(MICBIAS=2.5V)
Voltageregulation mV
At4-mAloadcurrent,page1/register46,
7
bitsD1–D0=01(MICBIAS=2V)
AudioADCDigitalDecimationFilterCharacteristics
SeeSection5.5.4.4foraudioADCdecimationfiltercharacteristics.
AUDIODAC
DACHeadphoneOutput,AC-coupledload=16Ω(single-ended),
drivergain=0dB,parasiticcapacitance=30pF
Full-scaleoutputvoltage(0
Outputcommon-modesetting=1.65V 0.707 Vrms
dB)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted(1) (2) 80 95 dB
THD Totalharmonicdistortion 0-dBFSinput –85 –65 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput –82 –60 dB
noise
Muteattenuation 87 dB
PSRR Power-supplyrejectionratio(3) RippleonHPVDD(3.3V)=200mVp-pat1kHz –62 dB
R =32Ω,THD+N≤–60dB 20
L
P Maximumoutputpower mW
O
R =16Ω,THD+N≤–60dB 60
L
DACLineout(HPDriverinLineoutMode)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted 95 dB
THD Totalharmonicdistortion 0-dBFSinput,0-dBgain –86 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput,0-dBgain –83 dB
noise
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
(3) DACtoheadphone-outPSRRmeasurementiscalculatedasPSRR=20×log(ΔV /ΔV ).
HPL HPVDD
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ElectricalCharacteristics(continued)
At25°C;AVDD,HPVDD,IOVDD=3.3V;SPLVDD,SPRVDD=3.6V;DVDD=1.8V;f (audio)=48kHz;
S
CODEC_CLKIN=256×f ;PLL=Off;VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DACDigitalInterpolationFilterCharacteristics
SeeSection5.6.1.4forDACinterpolationfiltercharacteristics.
DACOutputtoClass-DSpeakerOutput;Load=8Ω(Differential),50pF
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DAC
input=0dBFS,DACVCM(page1/register31,bits
2.2
D4–D3)=1.65V,class-Dgain=6dB,
Outputvoltage THD≤–16.5dB Vrms
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DAC
input=–2dBFS,DACVCM(page1/register31,bits 2.1
D4–D3)=1.65V,class-Dgain=6dB,THD≤–20dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DAC
Output,common-mode input=mute,DACVCM(page1/register31,bitsD4–D3) 1.8 V
=1.65V,class-Dgain=6dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,class-D
SNR Signal-to-noiseratio gain=6dB,measuredasidle-channelnoise,A-weighted 87 dB
(withrespecttofull-scaleoutputvalueof2.2Vrms)(1) (2)
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DAC
THD Totalharmonicdistortion input=–6dBFS,DACVCM(page1/register31,bits –67 dB
D4–D3)=1.65V,class-Dgain=6dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DAC
Totalharmonicdistortion+
THD+N input=–6dBFS,DACVCM(page1/register31,bits –66 dB
noise
D4–D3)=1.65V,class-Dgain=6dB
PSRR Power-supplyrejectionratio(3) SPLVDD=SPRVDD=3.6V,BTLmeasurement,rippleon –44 dB
SPLVDD/SPRVDD=200mVp-pat1kHz
Muteattenuation 110 dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DAC
VCM(page1/register31,bitsD4–D3)=1.65V,class-D 540
gain=18dB,THD=10%
mW
SPLVDD=SPRVDD=4.3V,BTLmeasurement,DAC
P Maximumoutputpower VCM(page1/register31,bitsD4–D3)=1.65V,class-D 790
O
gain=18dB,THD=10%
SPLVDD=SPRVDD=5.5V,BTLmeasurement,DAC
VCM(page1/register31,bitsD4–D3)=1.65V,class-D 1.29 W
gain=18dB,THD=10%
Output-stageleakagecurrent SPLVDD=SPRVDD=4.3V,deviceispowereddown
80 nA
fordirectbatteryconnection (power-up-resetcondition)
ADCandDACPOWERCONSUMPTION
ForADCandDACpowerconsumptionbasedonselectedprocessingblock,seeSection5.4.
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
(3) DACtospeaker-outPSRRisadifferentialmeasurementcalculatedasPSRR=20×log(ΔV /ΔV ).
SPL(P+M) SPLVDD
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ElectricalCharacteristics(continued)
At25°C;AVDD,HPVDD,IOVDD=3.3V;SPLVDD,SPRVDD=3.6V;DVDD=1.8V;f (audio)=48kHz;
S
CODEC_CLKIN=256×f ;PLL=Off;VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUT/OUTPUT
CMO
Logicfamily
S
0.7×
I =5μA,IOVDD≥1.6V
V IH IOVDD
IH
I =5μA,IOVDD<1.6V IOVDD
IH
0.3×
I =5μA,IOVDD≥1.6V –0.3 IOVD
IL
VIL D
Logiclevel V
I =5μA,IOVDD<1.6V 0
IL
0.8×
V I =2TTLloads
OH OH IOVDD
0.1×
V I =2TTLloads IOVD
OL OL
D
Capacitiveload 10 pF
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3.5 Timing Characteristics
3.5.1 I2S/LJF/RJF Timing in Master Mode
Allspecificationsat25°C,DVDD=1.8V
Note:Alltimingspecificationsaremeasuredat characterizationbutnottestedatfinaltest.
WCLK
t (WS) t
d r
BCLK
t (DO-WS) t (DO-BCLK) t
d d f
DOUT
t (DI) t (DI)
S h
DIN
T0145-08
IOVDD=1.1V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (WS) WCLKdelay 45 20 ns
d
t (DO-WS) WCLKtoDOUTdelay(forLJFmodeonly) 45 20 ns
d
t (DO-BCLK) BCLKtoDOUTdelay 45 20 ns
d
t(DI) DINsetup 8 6 ns
s
t (DI) DINhold 8 6 ns
h
t Risetime 25 10 ns
r
t Falltime 25 10 ns
f
Figure3-1.I2S/LJF/RJFTiminginMasterMode
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