Low Energy and Low Voltage ADC Design Strategy

69 Pages·2013·7.27 MB·English

1
Low Energy and Low Voltage
ADC Design Strategy
Akira Matsuzawa
Tokyo Institute of Technology
Outline
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• Overview of ADCs
• OpAmp based ADC design
• Comparator based ADC design : SAR ADCs
• Flash and sub-ranging ADCs
• Summary
ADC performance
3
Data rate is proportional to the product of f and N
s
Conversion frequency is determined by signal bandwidth.
f
D  Nf
BW  s
rate s
2
Shannon’s theory to determine capacity
Higher data-rate can be realized
by higher multi-level modulation.
 P 
C  BW log 1 S  It result in increase of ADC resolution.
 
2
P
 
N
1
SNR of ADC is
0.1
0.01 QPSK 16QAM 64QAM 256QAM
P 110 3
S  1.5  22N
110 4
P R
N ADC E 110 5
B6)
110 6
Therefore 110 7
110 8
f : Sampling frequency
C  Nf s 110 9
s N: Resolution 110 10
0 10 20 30 40
SNR (dB)
Performance and architectures of ADCs
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ADC has a suitable performance domain.
SAR ADC expands the performance area
) Comparator based
z Flash
1100GG
H
(
Sub-ranging
y
c
n
e 11GG
u
q
Pipeline
e
r
f OpAmp based
110000MM
n
o
i
s
r
1100MM
e
v
n
o
C
11MM
SAR Delta-sigma
110000kk
1100kk
44 66 88 1100 1122 1144 1166 1188
Resolution (bit)
Strategy of energy efficient ADC design
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Reducing static power
Resistor DAC  Capacitor DAC
OpAmp based  Dynamic comparator based
Reducing capacitance
2
E  CV
# of CMP Flash  Sub-range  SAR
d DD
1
TR size Large TR  Small TR with compensation
V 
T
C
G
Noise Use complementally ckt.
1
V 
n
C Clock Use self clocking
Reducing voltage
Effective to digital gates
Use forward or adaptive body biasing
SNR vs. signal bandwidth
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SNR of ADCs is inversely proportional to signal bandwidth, f .
b
 Higher bandwidth results in lower SNR and effective resolution.
SNR(dB )  SNR (dB ) 10 log f
0 b
90 BB
[[88]] VVCCOO
CC  P 
[[99]] VVCCOO
DD SNR(dB)  10log s 
[[1100]]CCTT
 
[[11EE11]]DDTT P
 
[[11FF22]]CCTT N
[[11GG33]]CCTT//DDTT
80 [[11HH44]]DDTT
P  P' (spectrumdensity) f
[[11II55]]CCTT N N b
[[11JJ66]]CCTT
[[11KK77]]DDTT
 P 
)
B SNR SNR(dB) 10log s  10log f
d 0 P'  b
(  
70 N
R
150 dB/Hz
N
S
SNR(dB)  SNR (dB)10log f
0 b
143 dB/Hz
60
135 dB/Hz
50
0.1 1 101 102
f (MHz)
b
SNR vs. signal bandwidth
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Same tendency to higher BW.
f =4f
s b
143dB
123dB
133dB
Timmy Sundstrom, PhD thesis, Linkoping 2011.
Fundamental Energy of sampling circuit
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Fundamental energy of sampling is often used. E  24kT 22N
s
However this neglects power for comparison.
Quantization voltage
V
V  FS
Sampling circuit qn 2N
Quantization noise power
Switch Capacitor
V 2 V 2
Signal P  qn  FS
qn 12 12  22N
C
C
V 2  P
Noise balance
n qn
Track Hold 22N
C  12kT
Capacitance
V 2
FS
Electrical energy=Thermal energy
P of sampling circuit
d
1 1 kT
CV 2  kT  V 2 
2 n 2 n C E  2CV 2  24kT 22N
d FS
Energy consumption of ADC
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Consumed energy of ADC is mainly determined by the resolution.
Energy of ADC is reaching 100x of the fundamental sampling energy,
and 10x of the fundamental ADC energy consumption.
Conventional fundamental sampling energy
E 2N
E  24kT 2
ADC
s s
E
s
E  22N 1019
s
Fundamental ADC conversion energy
involving energy consumption of comparator
E  N  E
ADC s
E  N  22N 1019
ADC
Timmy Sundstrom, PhD thesis, Linkoping 2011.
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OpAmp based ADC design