Logics and Models of Concurrent Systems PDF
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Logics and Models of Concurrent Systems NATO ASI Series Advanced Science Institutes Series A series presenting the results of activities sponsored by the NA TO Science Committee, which aims at the dissemination of advanced scientific and technological knowledge, with a view to strengthening links between scientific communities. The Series is published by an international board of publishers in conjunction with the NATO Scientific Affairs Division A Life Sciences Plenurn Publishing Corporation B Physics London and New York C Mathematical and D. Reidel Publishing Company Physical Sciences Dordrecht, Boston and Lancaster D Behavioural and Martinus Nijhoff Publishers Social Sciences Boston, The Hague, Dordrecht and Lancaster E Applied Sciences F Computer and Springer-Verlag Systems Sciences Berlin Heidelberg New York Tokyo G Ecological Sciences Series F: Computer and Systems Sciences Vol. 13 Logics and Models of Concurrent Systems Edited by Krzysztof R, Apt UTP, Universite Paris 7, 2, Place Jussleu 75251 Pans, France Springer-Verlag Berlin Heidelberg New York Tokyo Published in cooperation with NATO Scientific Affairs Division Proceedings of the NATO Advanced Study Institute on Logics and Models of Concurrent Systems held at La Colle-sur-Loup, France, 8-19 October 1984 ISBN-13:978-3-642-82455-5 e-ISBN-13:978-3-642-82453-1 001: 10.1007/978-3-642-82453-1 Library of Congress Cataloging in Publication Data. NATO Advanced Study Institute on Logics and Models of Concurrent Systems (1984: La Colle-sur-Loupe, France) Logics and models of concurrent systems. (NATO ASI series. Series F, Computer and system sciences; vol. 13) "Proceedings of the NATO Advanced Study Institute on Logics and Models of concurrent Systems held at La Colle- sur-Loupe, France, 8-19 October 1984"-T. p. verso. 1. Parallel processing (ElectroniC computers)--Congresses. 2. Electronic data processing-Distributed processing-Congresses. I. Apt. Krzysztof R., 1949-.11. Title. III. Series: NATO ASI series. Series F, Computer and system sciences; no. 13. QA76.5.N16 1984001.6485-8092 ISBN 0-387-15181-8 (U.S.) This work is subject to copyright. All rights are reserved, whether thewhole or part of the material is concerned, specifically those of translating, reprinting, re-use of illustrations, broadcastings, reproduction by photocopying machine or similar means, and storage in data banks. Under § 54 of the German Copyright Law where copies are made for other than private use, a fee is payable to "Verwertungsgesellschaft Wort", Munich. © Springer-Verlag Heidelberg 1985 Softcover reprint of the hardcover 1s t edition 1985 2145/3140-543210 Dear Reader, You took this book in your hands because you are interested in concurrency. I hope that it will not disappoint you. It constitutes proceedings of the Advanced Course "Logics and models for verification and specification of concurrent systems" which took place in La Colle-sur-Loup, close to Nice, in France from 8 to 19 October 1984. Some of the authors including the undersigned (see also page 244), sacrificed their vacation or part of it to meet the deadlines. Others kindly agreed to write a paper for this book even though they felt - contrary to our opinion - that the subject was already adequately treated in the literature (see e.g., page 72). The outcome is a volume containing 17 articles presenting an overview of the current research in the area of verification and specification of concurrent systems. It contains excellent contributions both in the form of survey papers and articles opening new directions. This book will enable you to become familiar with the current research in temporal logic, syntax directed verification methods, CCS, Theoretical CSP and other new topics. It is a great honour for me to be the editor of this book. Once again I would like to thank all the contributors for their effort and their cooperative spirit. Knysztof R. Apt CONTENTS Temporal logic E. M. Clarke, M. C. Browne, E. A. Emerson, A. P. Sistla, Using temporal logic for automatic verification of finite state systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 L. Fariaas~del-Cerro, Resolution modal logics 27 B. Hailpern, Tools for verifying network protocols 57 L. Lamport, An axiomatic semantics of concurrent programming languages 77 A. Pnueli, In transition from global to modular temporal reasoning about programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Syntax directed verification methods K. R. Apt, Correctness proofs of distributed termination algorithms 147 N. Francez, B. Hailpern, G. Taubenfe1d, Script: A communication abstraction mechanism and its verification 169 w. P. de Roever, The cooperation test: a syntax-directed verification method 213 Around CCS, Theoretical CSP and distributed systems G. Boudol, Notes on algebraic calculi of processes 261 S. Brookes, A. W. Roscoe, Deadlock analysis in networks of Communicating Processes 305 K. M. Chandy, J. Misra, A paradigm for detecting quiescent properties in distributed computations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Ph. Darondeau, About fair asynchrony 343 S. Graf, J. Sifakis, A logic for the specification and proof of controllable processes of CCS ........................................................... 369 VIII E.-R. Olderog, Specification-oriented programming in TCSP 397 Miscellaneous D. Gabbay, Theoretical foundations for non-monotonic reasoning in expert systems 439 J. Halpern, Y. Moses, Towards a theory of knowledge and ignorance: preliminary report 459 D. Harel, A. Pnueli, On the development of reactive systems 477 TEMPORAL LOGIC Using Temporal Logic for Automatic Verification of Finite State Systems E. M. Clarke Carnegie Mellon University M. C. Browne Carnegie Mellon University E. A. Emerson University of Texas,Austin A. P. Sistla University of Massachusetts, Amherst 1. Introduction. Temporal logic has been extensively investigated for proving properties of programs .. particularly for programs that involve nondeterminism or concurrency ([9], [11], [12]). However, most of the verification techniques developed so far involve manual construction of proofs, a task that may require a good deal of ingenuity and is usually quite tedious. In a series of papers ([1], [5], [6], [10» we have argued that proof construction is unnecessary in the case of finite state systems and can be replaced by a model theoretic approach which will mechanically determine if the system meets a specification expressed in a propositional temporal logic. In this paper we survey that work and give a detailed example of how our approach might be used in verifying a finite state hardware controller. The basic idea behind our approach is quite simple. The state· transition graph of a finite state system can be viewed as a finite Kripke structure, .and an efficient algorithm can be given to determine whether a structure is a model of a particular formula - i.e., to determine if the program meets its specification. The algorithm, which we call a model checker, is similar to the global flow analysis algorithms used in compiler optimization and has complexity linear in both the size of tlie structure and the size of the specification. When the number of states is not excessive (i.e. not more than a few thousand) we believe that our technique may provide a powerful debugging tool. Since our specification language is a branching·time temporal logic, it follows from ( [7], [8]) that our logic cannot, in general, express correctness of fair execution sequences. The alternative of using a linear time logic is ruled out because any model checker for such a logic must have high This research was supported by NSF Grants MCS·815553 and MCS·8302878. NATO AS! Series, Vol. F13 Logics and Models of Concurrent Systems Edited by K. R. Apt © Springer-Verlag Berlin Heidelberg 1985 4 complexity ([15]). We overcome this problem by moving fairness requirements into the semantics of our logic. Specifically, we change the definition of our basic modalities so that only fair paths are considered. Our previous model checking algorithm is modified to handle this extended logic without changing its complexity. An obviou& application for our method is in verifying complicated finite state systems that will ultimately be implemented as sequential circuits. Although this has been important problem for a long time. lack of any formal and efficient method of verification has prevented the creation of practical design aids. Since all the known techniques of simulation and prototype testing are time· consuming and not very reliable. there is an acute need for such tools. We illustrate our approach to this problem by verifying the correctness of a moderately tricky traffic controller expressed in a high· level state machine description language with a Pascal·like syntax (called SML). The output of the SML compiler can also be used to generate a PLA. PAL. or ROM .. thus, permitting state machines that have been verified by our techniques to be implemented as circuits. Most prior research on verifying finite state systems has involved some type of state reachability analysis. For example. in [16] and [18] reachability techniques are described for detection of system deadlocks, unspecified message receptions. and non·executable process interactions. An obvious advantage that our approach has over such methods is flexibility; our use of temporal logic provides a uniform notation for expressing a wide variety of correctness properties. Furthermore, it is unnecessary to formulate all of the specifications as reachability assertions since the model checker can handle both safety and liveness properties with equal facility. Perhaps the research that is most closely related to our own is that of Quielle and Sifakis ([13], [14]), who have independently developed a system which will automatically check that a finite state CSP program satisfies a specification in temporal logic. The logical system that is used in [13], is not as expressive as our logic, however. and no attempt is made to handle fairness properties. Although fairness is discussed in [14], the approach that is used is much different from the one that we have adopted. Special temporal operators are introduced for asserting that a property must hold on fair paths. but neither a complexity analysis nor an efficient model checking algorithm is given for the extended logiC. Our paper is organized as follows: Section 2 contains the syntax and semantics of our logic. In Section 3 fixpoint characterizations are given for the various temporal operators. The fixpoint characterization are used in Section 4 to develop the basic model checking algorithm. An extension of the algorithm which only considers fair computations is discussed in section 5. In section 6 we
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