Logic Synthesis for Asynchronous Controllers and Interfaces

278 Pages·2002·9.16 MB·English

by  Prof. J. Cortadella, Dr. M. Kishinevsky, Dr. A. Kondratyev, Prof. L. Lavagno, Prof. A. Yakovlev (auth.)

Springer Series in
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1 Cellular Neural Networks
Chaos, Complexity and VLSI Processing
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2 Technology ofIntegrated Circuits
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6 High-Frequency Bipolar Transistors
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8 Logic Synthesis for Asynchronous Controllers and Interfaces
By J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev
Series homepage - http://www.springer.de/phys/books/ ssam/
J. Cortadella M. Kishinevsky
A. Kondratyev L. Lavagno A. Yakovlev
Logic Synthesis
for Asynchronous Controllers
and Interfaces
With 146 Figures
, Springer
Prof. J. Cortadella Prof. L. Lavagno
Department of Software Dipartimento di Elettronica
Universitat Politecnica de Catalunya Politecnico di Torino
Campus Nord. Modul C6 Corso Duca degli Abruzzi 24
08034 Barcelona, Spain 10129 Torino, Italy
Dr. M. Kishinevsky Prof. A. Yakovlev
Intel Corporation Department of Computing Science
JF4-211, 2111 N.E. 25th Ave. University of Newcastle upon Tyne Claremont
Hillsboro, OR 97124-5961, USA Tower, Claremont Road
Newcastle upon Tyne, NE1 7RU, U.K.
Dr. A. Kondratyev
Cadence Design Systems
2001 Addison Avenue
Berkeley, CA 94704, USA
Series Editors:
Dr. Kiyoo Itoh
Hitachi Ltd., Central Research Laboratory, 1-280 Higashi-Koigakubo
Kokubunji-shi, Tokyo 185-8601, Japan
Professor Thomas Lee
Stanford University, Department of Electrica! Engineering, 420 Via Palou Mall, CIS-205
Stanford, CA 94305-4070, USA
Professor Takayasu Sakurai
Center for Collaborative Research, University of Tokyo, 7-22-1 Roppongi
Minato-ku, Tokyo 106-8558, Japan
Professor Doris Schmitt-Landsiedel
Technische Universităt Munchen, Lehrstuhl fiir Technische Elektronik
Theresienstrasse 90, Gebăude N3, 80290 Munchen, Germany
ISSN 1437-0387
ISBN 978-3-642-62776-7 ISBN 978-3-642-55989-1 (eBook)
DOI 10.1007/978-3-642-55989-1
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Logic synthesis for asynchronous controllers and interfaces 1 ). Cortadella .... -Berlin; Heidelberg; New York;
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To Cristina, Viviana, Kamal,
Lena, Katie, Gene, Masha, Anna,
Mitya, Paola, Maria, and Gregory,
who sometimes waited patiently at home,
sometimes joined in the fun.
Preface
This book is the result of a long friendship, of a broad international co-
operation, and of a bold dream. It is the summary of work carried out by
the authors, and several other wonderful people, during more than 15 years,
across 3 continents, in the course of countless meetings, workshops and discus-
sions. It shows that neither language nor distance can be an obstacle to close
scientific cooperation, when there is unity of goals and true collaboration.
When we started, we had very different approaches to handling the mys-
terious, almost magical world of asynchronous circuits. Some were more theo-
retical, some were closer to physical reality, some were driven mostly by design
needs. In the end, we all shared the same belief that true Electronic Design
Automation research must be solidly grounded in formal models, practically
minded to avoid excessive complexity, and tested "in the field" in the form
of experimental tools. The results are this book, and the CAD tool petrify.
The latter can be downloaded and tried by anybody bold (or desperate)
enough to tread into the clockless (but not lawless) domain of small-scale
asynchronicity. The URL is http://www.lsi. upc. esr j ordic/petrify.
We believe that asynchronous circuits are a wonderful object, that aban-
dons some of the almost militaristic law and order that governs synchronous
circuits, to improve in terms of simplicity, energy efficiency and performance.
To use a social and economic parable, strict control and tight limits are sim-
ple ways to manage large numbers of people, but direct loose interaction
is the best known means to quickly and effectively achieve complex goals.
In both cases, social sciences and logic circuits, speed and efficiency can be
conjugated by keeping the interaction local. Modularity is the key to solving
complex problems by preserving natural boundaries.
Of course, a good deal of automation is required to keep any complex
design problem involving millions of entities under control. This book con-
tains the theory and the algorithms that can be, and have been, used to
create a complete synthesis environment for the synthesis of asynchronous
circuits from high-level specifications to a logic circuit. The specification can
be derived with relative ease from a Register Transfer Level-like model of
the required functionality. The circuit is guaranteed to work regardless of the
delays of the gates and of some wires.
VIII Preface
Unfortunately asynchronous circuits must pay something for the added
freedom they provide: algorithmic complexity. Logic synthesis can no longer
use Boolean algebra, but must resort to sequential Finite State Machine-
like models, which are much more expensive to manipulate. Fortunately the
intrinsic modularity of the asynchronous paradigm comes to rescue again,
since relatively small blocks can be implemented independent of each other,
without affecting correctness.
It is not clear today whether asynchronous circuits will ever see widespread
adoption in everyday industrial design practice. One serious problem is the
requirement to "think different" when designing them. One must consider
causality relations rather than fixed steps. However, this book shows that
once this conceptual barrier is overcome, due e.g. to the rise of unavoidable
problems with the synchronous design style, it is indeed possible to define
and implement a synthesis-based design flow that ensures enough designer
productivity.
We all hope, thus, that our work will soon be used in practical designs.
So far it has been a very challenging, fruitful and exciting cooperation.
The list of people and organizations that deserve our gratitude is long
indeed. First of all, some colleagues helped with the formulation and the
implementation of several ideas described in this book. Alexander Taubin
(Theseus Research) contributed heavily to the topic of synthesis from STGs.
Shai Rotem initiated and Ken Stevens and Steven M. Burns (all from Intel
Strategic CAD Lab) contributed to the research on relative timing synthe-
sis. Enric Pastor (Universitat Politecnica de Catalunya) cooperated on logic
decomposition and technology mapping. Then, we would like to acknowledge
support from Intel Corporation and various funding agencies such as: ES-
PRIT ACiD-WG Nr. 21949, EPSRC grant GR/M94366, MURST research
project "VLSI architectures", CICYT grants TIC98-0410 and TIC98-0949.
Finally, all members of the asynchronous community, both users and op-
ponents of the STG-based approach, and in particular the users of petrify,
provided us with excellent feedback.
Barcelona, Spain, Jordi Cortadella
Hillsboro, Oregon, Michael Kishinevsky
San Jose, California, Alex Kondratyev
Torino, Italy, Luciano Lavagno
Newcastle upon Tyne, United Kingdom, Alexandre Yakovlev
October, 2001
Contents
1. Introduction.............................................. 1
1.1 A Little History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Advantages of Asynchronous Logic ....................... 3
1.2.1 Modularity...................................... 3
1.2.2 Power Consumption and Electromagnetic Interference. 4
1.2.3 Performance..................................... 6
1.3 Asynchronous Control Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1 Delay Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10
1.3.2 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11
2. Design Flow. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. 13
2.1 Specification of Asynchronous Controllers. . . . . . . . . . . . . . . . .. 13
2.1.1 From Timing Diagrams to Signal Transition Graphs.. 14
2.1.2 Choice in Signal Transition Graphs. . . . . . . . . . . . . . . .. 15
2.2 Transition Systems and State Graphs. . . . . . . . . . . . . . . . . . . .. 16
2.2.1 State Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16
2.2.2 Binary Interpretation. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 17
2.3 Deriving Logic Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
2.3.1 System Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 19
2.3.2 Excitation and Quiescent Regions .................. 19
2.3.3 Next-state Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 20
2.4 State Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 21
2.5 Logic Decomposition and Technology Mapping. . . . . . . . . . . .. 23
2.6 Synthesis with Relative Timing. . . . . . . . . . . . . . . . . . . . . . . . . .. 25
2.7 Summary.............................................. 27
3. Background.............................................. 29
3.1 Petri Nets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
3.1.1 The Dining Philosophers. . . . . . . . . . . . . . . . . . . . . . . . .. 31
3.2 Structural Theory of Petri Nets . . . . . . . . . . . . . . . . . . . . . . . . .. 37
3.2.1 Incidence Matrix and State Equation. . . . . . . . . . . . . .. 37
3.2.2 Transition and Place Invariants .. . . . . . . . . . . . . . . . . .. 38
3.3 Calculating the Reachability Graph of a Petri Net . . . . . . . . .. 39
3.3.1 Encoding........................................ 41
X Contents
3.3.2 Transition Function and Reachable Markings ........ 42
3.4 Transition Systems ..................................... 44
3.5 Deriving Petri Nets from Transition Systems. . . . . . . . . . . . . .. 45
3.5.1 Regions......................................... 45
3.5.2 Properties of Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 47
3.5.3 Excitation Regions ............................... 47
3.5.4 Excitation-Closure................................ 48
3.5.5 Place-Irredundant and Place-Minimal Petri Nets. . . .. 49
3.6 Algorithm for Petri Net Synthesis ........................ 52
3.6.1 Generation of Minimal Pre-regions ................. 53
3.6.2 Search for Irredundant Sets of Regions. . . . . . . . . . . . .. 54
3.6.3 Label Splitting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55
3.7 Event Insertion in Transition Systems. . . . . . . . . . . . . . . . . . . .. 57
4. Logic Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 61
4.1 Signal Transition Graphs and State Graphs. . . . . . . . . . . . . . .. 62
4.1.1 Signal Transition Graphs. . . . . . . . . . . . . . . . . . . . . . . . .. 62
4.1.2 State Graphs .................................... 64
4.1.3 Excitation and Quiescent Regions .................. 65
4.2 Implementability as a Logic Circuit. . . . . . . . . . . . . . . . . . . . . .. 66
4.2.1 Boundedness..................................... 66
4.2.2 Consistency..................................... 67
4.2.3 Complete State Coding ........................... 69
4.2.4 Output Persistency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 70
4.3 Boolean Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 73
4.3.1 ON, OFF and DC Sets. . . . . . . . . . . . . . . . . . .. . . . . . . .. 73
4.3.2 Support of a Boolean Function. . . . . . . . . . . . . . . . . . . .. 73
4.3.3 Cofactors and Shannon Expansion. . . . . . . . . . . . . . . . .. 74
4.3.4 Existential Abstraction and Boolean Difference. . . . . .. 74
4.3.5 Dnate and Binate Functions. . . . . . . . . . . . . .. . . . . . . .. 74
4.3.6 Function Implementation. . . . . . . . . . . . . . . . . . . . . . . . .. 74
4.3.7 Boolean Relations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 75
4.4 Gate Netlists .......................................... 75
4.4.1 Complex Gates .................................. 76
4.4.2 Generalized C-Elements . . . . . . . . . . . . . . . . . .. . . . . . . .. 76
4.4.3 C-Elements with Complex Gates. . . . . . . . . .. . . . . . . .. 78
4.5 Deriving a Gate Netlist ................................. 79
4.5.1 Deriving Functions for Complex Gates . . . . . . . . . . . . .. 79
4.5.2 Deriving Functions for Generalized C-Elements. . . . . .. 81
4.6 What is Speed-Independence? . . . . . . . . . . . . . . . . . . .. . . . . . . .. 82
4.6.1 Characterization of Speed-Independence. . . .. . . . . . . .. 85
4.6.2 Related Work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 85
4.7 Summary.............................................. 86
Contents XI
5. State Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87
5.1 Methods for Complete State Coding. . . . . . . . . . . . . . . . . . . . .. 91
5.2 Constrained Signal 1tansition Event Insertion. . . . . . . . . . . . .. 94
5.2.1 Speed-Independence Preserving Insertion. . . . . . . . . . .. 95
5.3 Selecting SIP-Sets ...................................... 101
5.4 1tansformation of State Graphs .......................... 103
5.5 Completeness of the Method ............................. 107
5.6 An Heuristic Strategy to Solve esc ....................... 115
5.6.1 Generation of I-Partitions ......................... 115
5.6.2 Exploring the Space of I-Partitions ................. 116
5.6.3 Increasing Concurrency ........................... 117
5.7 Cost Function .......................................... 118
5.7.1 Estimation of Logic ............................... 119
5.7.2 Examples of esc Conflict Elimination .............. 119
5.8 Related Work .......................................... 122
5.9 Summary .............................................. 123
6. Logic Decomposition ..................................... 125
6.1 Overview .............................................. 126
6.2 Architecture-Based Decomposition ........................ 132
6.3 Logic Decomposition Using Algebraic Factorization ......... 134
6.3.1 Overview ........................................ 134
6.3.2 Combinational Decomposition ..................... 135
6.3.3 Hazard-Free Signal Insertion ....................... 137
6.3.4 Pruning the Solution Space ........................ 138
6.3.5 Finding a Valid Excitation Region .................. 139
6.3.6 Progress Analysis ................................ 141
6.3.7 Local Progress Conditions ......................... 142
6.3.8 Global Progress Conditions ........................ 145
6.4 Logic Decomposition Using Boolean Relations .............. 146
6.4.1 Overview ........................................ 148
6.4.2 Specifying Permissible Decompositions with BRs ..... 150
6.4.3 Functional Representation of Boolean Relations . . . . . . 154
6.4.4 Two-Level Sequential Decomposition ................ 155
6.4.5 Heuristic Selection of the Best Decomposition ........ 160
6.4.6 Signal Acknowledgment and Insertion ............... 160
6.5 Experimental Results ................................... 161
6.5.1 The Cost of Speed Independence ................... 163
6.6 Summary .............................................. 164
7. Synthesis with Relative Timing . .......................... 167
7.1 Motivation ............................................ 167
7.1.1 Synthesis with Timing ............................ 169
7.1.2 Why Relative Timing? ............................ 169
7.1.3 Abstraction of Time .............................. 170