LMH0031 SMPTE 292M/259M Dig Video Deserial/Descram w/Video & Ancillary Data FIFO

39 Pages·2013·0.36 MB·English

LMH0031
www.ti.com SNLS218A–JANUARY2006–REVISEDAPRIL2013
LMH0031 SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video
and Ancillary Data FIFOs
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FEATURES APPLICATIONS
1
• SDTV/HDTVSerialDigitalVideoStandard • SDTV/HDTVSerial-to-Parallel Digital Video
2
Compliant Interfacesfor:
• Supports270Mbps,360Mbps,540Mbps, – VideoEditingEquipment
1.483Gbpsand1.485GbpsSerialVideoData – VTRs
RateswithAuto-Detection
– StandardsConverters
• LSBDe-DitheringOption
– Digital VideoRouters andSwitchers
• UsesLow-Cost27MHzCrystalor Clock
– Digital VideoProcessingandEditing
OscillatorReference
Equipment
• FastVCOLockTime:<500 µsat1.485Gbps
– VideoTestPatternGeneratorsandDigital
• Built-inSelf-Test(BIST)andVideoTestPattern VideoTestEquipment
Generator(TPG)
– VideoSignalGenerators
(1) PatentApplicationsMadeorPending
• AutomaticEDH/CRCWordand Flag DESCRIPTION
Processing The LMH0031 SMPTE 292M / 259M Digital Video
• AncillaryDataFIFOwithExtensivePacket Deserializer/Descrambler with Video and Ancillary
Data FIFOs is a monolithic integrated circuit that
HandlingOptions
deserializes and decodes SMPTE 292M, 1.485Gbps
• Adjustable,4-DeepParallelOutputVideoData
(or 1.483Gbps) serial component video data, to 20-bit
FIFO parallel data with a synchronized parallel word-rate
• FlexibleControl and ConfigurationI/OPort clock. It alsodeserializesanddecodesSMPTE 259M,
270Mbps, 360Mbps and SMPTE 344M (proposed)
• LVCMOSCompatibleControl Inputsand Clock
540Mbps serial component video data, to 10-bit
andDataOutputs
parallel data. Functions performed by the LMH0031
• LVDSandECL-Compatible,Differential,Serial include: clock/data recovery from the serial data,
Inputs serial-to-parallel data conversion, SMPTE standard
• 3.3VI/OPowerSupplyand 2.5VLogicPower datadecoding, NRZI-to-NRZconversion,paralleldata
SupplyOperation clock generation, word framing, CRC and EDH data
checking and handling, Ancillary Data extraction and
• LowPower: Typically850mW
automatic video format determination. The parallel
• 64-PinTQFP Package video output features a variable-depth FIFO which
• CommercialTemperatureRange0°Cto+70°C can be adjusted to delay the output data up to 4
parallel data clock periods. Ancillary Data may be
selectively extracted from the parallel data through
the use of masking and control bits in the
configuration and control registers and stored in the
on-chip FIFO. Reverse LSB dithering is also
implemented.
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
Alltrademarksarethepropertyoftheirrespectiveowners.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2013,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
LMH0031
SNLS218A–JANUARY2006–REVISEDAPRIL2013 www.ti.com
DESCRIPTION (CONTINUED)
The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the
configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to
the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a
reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply
rejectionandnoiseperformance.
The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables
comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD
component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical
colourbarpattern,forallimplementedrasters. Thecolour barpatternhasoptionaltransitioncodingatchangesin
thechromaandlumabardata.TheTPGdataisoutput viatheparalleldataport.
The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable
Driver,istheidealcomplementtotheLMH0031.
The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power
dissipationistypically850mW.Thedeviceispackagedina64-pinTQFP.
TYPICAL APPLICATION
VDD
75: SMPTE 292M
SMPTE Video 1% or 259M
Data Input Serial Data
LMH0030
SD/HD Encoder/ Serializer/
Cable Driver
Parallel Ancilliary 1 PF
Data Input
75: Coaxial Cable
1 PF
LMH0034
Adaptive Cable
Equalizer
75:
1%
SMPTE Video
Data Output
LMH0031
SD/HD Decoder/
Deserializer
Parallel Ancilliary
Data Output
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Block Diagram
XTALi/Ext
Clk
XTALo REFERENCE CLOCK/OSCILLATOR
PLL/CLOCK SYSTEM
PCLK
SDI
INPUT DATA SAMPLERS
CLOCK/DATA RECOVERY
SDI
BIST & TPG
RBB
SDI
RREF BIAS
TRS &
SMPTE NRZI-NRZ CONVERTER PCLK FORMAT
DESCRAMBLER/
DETECTOR
DESERIALIZER
EDH / CRC
DE-DITHERING GENERATORS/CHECKERS
US US
B B
R A
E T
T A
S D
ANCILLIARY MA O FRAMING
AD[9:0] DATA FIFO VIDE CONTROL
ACLK
RD / WR CONFIGURATION
& CONTROL DV[19:10]
REGISTERS
ANC / CTRL
VIDEO DATA
FIFO & OUTPUT
DV[9:0]
VCLK
I/O[7:0] MULTI-FUNCTION I/O PORT
PCLK
SYSTEM
RESET RESET
MASTER
CONTROL
INT. RESET CONTROLLER
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Connection Diagram
5O 6O 7O KLCA VDDD 0DA 1DA 2DA 3DA 4DA VDSS 5DA 6DA 7DA 8DA 9DA
I I I
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
IO4 17 64 RD/WR
IO3 18 63 ANC/CTRL
IO2 19 62 VDDD
V 20 61 XTALo
SSIO
DV19 21 60 XTALi/Ext Clk
DV18 22 59 V
SSIO
DV17 23 58 VDDSI
DV16 24 57 SDI
LMH0031
DV15 25 56 SDI
V 26 55 V
DDIO SSSI
DV14 27 54 RBB
DV13 28 53 R
REF
DV12 29 52 VSSPLL
DV11 30 51 VDDPLL
DV10 31 50 VCLK
V 32 49 RESET
SSD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
VDDD 9VD 8VD 7VD 6VD 5VD VDSS 4VD 3VD 2VD 1VD 0VD 1OI 0OI VOISS VOIDD
Figure1. 64-PinTQFP
SeePackageNumber PAG0064A
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Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
Absolute Maximum Ratings(1)(2)
CMOSI/OSupplyVoltage(V –V ): 4.0V
DDIO SSIO
SDISupplyVoltage(V –V ): 4.0V
DDSI SSSI
DigitalLogicSupplyVoltage(V –V ): 3.0V
DDD SSD
PLLSupplyVoltage(V –V ): 3.0V
DDPLL SSPLL
CMOSInputVoltage(Vi): V −0.15VtoV
SSIO DDIO
+0.15V
CMOSOutputVoltage(Vo): V −0.15VtoV
SSIO DDIO
+0.15V
CMOSInputCurrent(singleinput): Vi=V −0.15V: −5mA
SSIO
Vi=V +0.15V: +5mA
DDIO
CCMMOOSSOOuuttppuuttSSoouurrccee//SSiinnkkCCuurrrreenntt:: ±±66mmAA
I OutputCurrent: +300μA
BB
I OutputCurrent: +300μA
REF
SDIInputVoltage(Vi): V −0.15VtoV
SSSI DDSI
+0.15V
PackageThermalResistance θ @0LFMAirflow 40.1°C/W
JA
θ @500LFMAirflow 24.5°C/W
JA
θ 5.23°C/W
JC
StorageTemp.Range: −65°Cto+150°C
JunctionTemperature: +150°C
LeadTemperature(Soldering4Sec): +260°C
ESDRating(HBM): 6.0kV
ESDRating(MM): 400V
(1) AbsoluteMaximumRatingsarethoseparametervaluesbeyondwhichthelifeandoperationofthedevicecannotbeensured.The
statinghereinofthesemaximumsshallnotbeconstruedtoimplythatthedevicecanorshouldbeoperatedatorbeyondthesevalues.
Thetableof“ElectricalCharacteristics”specifiesacceptabledeviceoperatingconditions.
(2) Itisanticipatedthatthisdevicewillnotbeofferedinamilitaryqualifiedversion.IfMilitary/Aerospacespecifieddevicesarerequired,
pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityandspecifications.
Recommended Operating Conditions
Symbol Parameter Conditions Reference Min Typ Max Units
V CMOSI/OSupplyVoltage V −V
DDIO DDIO SSIO
3.150 3.300 3.450 V
V SDISupplyVoltage V −V
DDSD DDSI SSSI
V DigitalLogicSupplyVoltage V –V
DDD DDD SSD
2.375 2.500 2.625 V
V PLLSupplyVoltage V –V
DDPLL DDPLL SSPLL
OperatingFreeAir
T 0 +70 °C
A Temperature
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Required Input Conditions(1)(2)
Symbol Parameter Conditions Reference Min Typ Max Units
VIN InputVoltageRange AllLVCMOS VSSIO VDDIO V
t,t RiseTime,FallTime 10%–90% Inputs 1.0 1.5 3.0 ns
r f
SMPTE259M,LevelC 270
SMPTE259M,LevelD 360
BR SerialInputDataRate SMPTE344M SDI,SDI 540 M
SDI BPS
SMPTE292M 1,483
SMPTE292M 1,485
V V
V CommonModeVoltage V =125mV SSSI DDSI V
CM(SDI) IN P-P +1.0V −0.05V
V SDISerialInputVoltage,
IN(SDI) 125 800 880 mV
Single-ended P-P
V SDISerialInputVoltage,
IN(SDI) SDI,SDI 125 800 880 mV
Differential P-P
20%–80%,SMPTE259M
0.4 1.0 1.5 ns
DataRates
t,t RiseTime,FallTime
r f
20%–80%,SMPTE292M
270 ps
DataRates
Ancillary/ControlDataClock
f V MHz
ACLK Frequency CLK
DC DutyCycle,AncillaryClock A 45 50 55 %
ACLK CLK
Ancillary/ControlClockand
t,t 10%–90% 1.0 1.5 3.0 ns
r f DataRiseTime,FallTime
SetupTime,AD toA or
t N CLK 3.0 1.5 ns
S IONtoACLKRisingEdge ControlDataInputor ION,ADN,ACLK
HoldTime,RisingEdgeA I/OBusInput TimingDiagram
t CLK 3.0 1.5 ns
H toAD orA toIO
N CLK N
BiasSupplyReference
R Tolerance1% 4.75k Ω
REF Resistor
fEXTCLK ExternalClockFrequency ExtClk −100 +100
27.0 MHz
f CrystalFrequency SeeFigure7 XTALo,XTALi ppm ppm
XTAL
(1) RequiredInputConditionsaretheelectricalsignalconditionsorcomponentvalueswhichshallbesuppliedbythecircuitinwhichthis
deviceisusedinorderforittoproducethespecifiedDCandACelectricaloutputcharacteristics.
(2) FunctionalandcertainotherparametrictestsutilizeaLMH0030astheinputsourcetotheSDIinputsoftheLMH0031.TheLMH0030is
DCcoupledtotheinputsoftheLMH0031.TypicalV =800mV,V =2.9V.
IN CM
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DC Electrical Characteristics
OverSupplyVoltageandOperatingTemperatureranges,unlessotherwisespecified(1)(2).
Symbol Parameter Conditions Reference Min Typ Max Units
V InputVoltageHighLevel 2.0 V
IH DDIO
V
VIL InputVoltageLowLevel AllLVCMOS VSSIO 0.8
I InputCurrentHighLevel V =V (3) Inputs +85 +150
IH IH DDIO
µA
I InputCurrentLowLevel V =V −1 −20
IL IL SSIO
V OutputVoltageHighLevel I =−2mA 2.4 2.7 V
OH OH DDIO
V V
V OutputVoltageLowLevel I =+2mA V SSIO SSIO
OL OL SSIO +0.3 +0.5V
AllLVCMOS
V MinimumDynamicV I =−2mA (4) Outputs VDDIO V
OHV OH OH −0.5
V MaximumDynamicV I =+2mA (4) VSSIO
OLP OL OL +0.4
V SerialDataInputVoltage 125 800 880 mV
SDI P-P
I SerialDataInputCurrent SDI,SDI ±1 ±10 µA
SDI
V InputThereshold OverVCMrange <100 mV
TH
I BiasSupplyOutputCurrent R =8.66kΩ1% −220 −188
BB BB
µA
I ReferenceOutputCurrent R =4.75kΩ1% −290 −262
REF REF
PowerSupplyCurrent,3.3V 270MBPSDataRate 38.0 45.0
I (3.3V) V ,V mA
DD Supply,Total 1,485M DataRate DDIO DDSI 47.0 50.0
BPS
PowerSupplyCurrent,2.5V 270MBPSDataRate 80 120
I (2.5V) V ,V mA
DD Supply,Total 1,485M DataRate DDD DDPLL 220 340
BPS
(1) Currentflowintodevicepinsisdefinedaspositive.Currentflowoutofdevicepinsisdefinedasnegative.Allvoltagesarereferencedto
V =V =V =0V.
SSIO SSD SSSI
(2) TypicalvaluesarestatedforV =V =+3.3V,V =V =+2.5VandT =+25°C.
DDIO DDSI DDD DDPLL A
(3) I includesstaticcurrentrequiredbyinputpull-downdevices.
IH
(4) V andV aremeasuredwithrespecttoreferenceground.V isthepeakoutputLOWvoltageorgroundbouncethatmayoccur
OHV OLP OLP
underdynamicsimultaneousoutputswitchingconditions.V isthelowestoutputHIGHvoltageoroutputdroopthatmayoccurunder
OHV
dynamicsimultaneousoutputswitchingconditions.
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AC Electrical Characteristics
OverSupplyVoltageandOperatingTemperatureranges,unlessotherwisespecified(1).
Symbol Parameter Conditions Reference Min Typ Max Units
SerialVideoDataInputs
SMPTE259M,LevelC 270
SMPTE259M,LevelD 360
BR SerialInputDataRate SMPTE344M 540 M
SDI BPS
SMPTE292M 1,483
SDI,SDI
SMPTE292M 1,485
20%–80%,SMPTE259M
0.4 1.0 1.5 ns
DataRates
t,t RiseTime,FallTime
r f
20%–80%,SMPTE292M
270 ps
DataRates
ParallelVideoDataOutputs
SMPTE259M,270M 27.0
BPS
SMPTE267M,360M 36.0
BPS
VideoOutputClock
f SMPTE344M,540M V 54.0 MHz
VCLK Frequency BPS CLK
SMPTE292M,1,483M 74.176
BPS
SMPTE292M,1,485M 74.25
BPS
PropagationDelay,Video V toDV
t 50%–50% CLK N 0.5 2.0 ns
pd ClocktoVideoDataValid TimingDiagram
DC DutyCycle,VideoClock V 50±5 %
V CLK
27MHz 2.0
VideoDataOutputClock 36MHz 1.4
t V ns
JIT Jitter 54MHz CLK 1.0 P-P
74.25MHz 0.5
ParallelAncillary/ControlDataInputs,Multi-functionParallelBusInputs
Ancillary/ControlDataClock
f V MHz
ACLK Frequency CLK
A
CLK
DC DutyCycle,AncillaryData ANCDataclock (2) 45 50 55 %
A Clock
t,t OutputRiseTime,FallTime 10%–90% 1.0 1.5 3.0
r f
SetupTime,AD toA or
t N CLK IO ,AD ,A 3.0 1.5
S IONtoACLKRisingEdge ControlDataInputorI/OBus TimNingDNiagCraLmK ns
HoldTime,RisingEdgeA Input
t CLK 3.0 1.5
H toAD orA toIO
N CLK N
ParallelAncillary/ControlDataOutputs
PropagationDelay,Clockto
t 8.5
pd ControlData A toAD
50%–50% CLK N ns
PropagationDelay,Clockto TimingDiagram
t 11.5
pd AncillaryData
Multi-functionParallelI/OBus
IO0–IO7
t,t RiseTime,FallTime 10%–90% 1.0 1.5 3.0 ns
r f TimingDiagram
PLL/CDR,FormatDetect
SDRates(3) 0.32 1.0
t LockDetectTime
LOCK HDRates(3) 0.26 1.0 ms
t FormatDetectTime AllRates 20
FORMAT
(1) TypicalvaluesarestatedforV =V =+3.3V,V =V =+2.5VandT =+25°C.
DDIO DDSI DDD DDPLL A
(2) WhenusedtoclockcontroldataintoorfromtheLMH0031,thedutycyclerestrictiondoesnotapply.
(3) Measuredfromrising-edgeoffirstSDIcycleuntilLockDetectbitgoeshigh(true).LocktimeincludesCDRphaseacquisitiontimeplus
PLLlocktime.
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Test Loads
V
DDIO
I
OL
Hi-Z test eqpt. t 5k:
S
1 (attenuation 0dB)
CMOS
outputs
C I
L OH
S
2
C including probe and jig
L
capacitance, 3pF max.
S - open, S - closed for V measurement
1 2 OH
S - closed, S - open for V measurement
1 2 OL
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Test Circuit
SDI
1.0 PF +2.5 Vdc
(x4) 0.1 (x2) 0.1 PF
PF
4.7 PF
82.5: 4.7 PF
1 nF 825: (x4) 16V (x2) 16V
+3.3 Vdc
12, 33,
SDI
62 51 58 26, 48
1.0 PF
57 SDI VDDD DDPLL VDDSI VDDIO VCLK 50
82.5: 825: V 3.3V
56 44
8.66k SDI 2.5V Supply DV0
54 Supply 43
RBB DV1
53 42
RREF DV2
4.75k 61 41
XTALo DV3
27 MHz 60 XTALi/EXT CLK HD Chroma, DV4 40
CLK. I/P SD Luma &
46 38
IO0 Chroma DV5
45 37
IO1 DV6
19 36
IO2 DV7
Multi- 18 35
IO3 DV8
function
17 34
I/O Bus IO4 DV9
16 31
IO5 LMH0031 DV10
15 30
IO6 DV11
14 29
IO7 DV12
13 28
ACLK DV13
11 27
AD0 DV14
10 HD Luma 25
AD1 DV15
9 24
AD2 DV16
8 23
AD3 DV17
Ancilliary/ 7 22
AD4 DV18
Control Bus
5 21
AD5 DV19
4 63
AD6 ANC / CTRL
3 64
AD7 RD / WR
2 2.5V 49
AD8 Supply 3.3V RESET
1 Supply
AD9 VSSD VSSPLL VSSSI VSSIO
6, 32, 52 55 20, 47,
39 59 Output loads
0 Vdc
omitted for clarity.
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