Lecture 7 Memory And Array Circuits - Imperial College London

100 Pages·2006·1.27 MB·English

Lecture 7
Memory and Array Circuits
Konstantinos Masselos
Department of Electrical & Electronic Engineering
Imperial College London
URL: http://cas.ee.ic.ac.uk/~kostas
E-mail: [email protected]
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 1
Based on slides/material by…
J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
(cid:139)
“Digital Integrated Circuits: A Design Perspective”, Prentice Hall
D. Harris http://www.cmosvlsi.com/coursematerials.html
(cid:139)
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems
Perspective”, Addison Wesley
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 2
Recommended Reading
J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”:
(cid:139)
Chapter 12
Weste and Harris, “CMOS VLSI Design: A Circuits and Systems
(cid:139)
Perspective”: Chapter 11
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 3
Outline
Memory classification
(cid:139)
Basic building blocks
(cid:139)
ROM
(cid:139)
Non Volatile Read Write Memories
(cid:139)
Static RAM (SRAM)
(cid:139)
Dynamic RAM (DRAM)
(cid:139)
Memory peripheral circuit
(cid:139)
Content Addressable Memory (CAM)
(cid:139)
Serial access memories
(cid:139)
Programmable Logic Array
(cid:139)
Reliability and Yield
(cid:139)
Memory trends
(cid:139)
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 4
Semiconductor Memory Classification
RWM NVRWM ROM
Random Non-Random
EPROM
Mask-Programmed
Access Access
2
E PROM
Programmable (PROM)
SRAM FIFO FLASH
LIFO
DRAM
Shift Register
CAM
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 5
Memory Arrays
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory
(CAM)
Read/Write Memory Read Only Memory
Shift Registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)
Serial In Parallel In First In Last In
Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)
Mask ROM Programmable Erasable Electrically Flash ROM
ROM Programmable Erasable
(PROM) ROM Programmable
(EPROM) ROM
(EEPROM)
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 6
Outline
Memory classification
(cid:139)
Basic building blocks
(cid:139)
ROM
(cid:139)
Non Volatile Read Write Memories
(cid:139)
Static RAM (SRAM)
(cid:139)
Dynamic RAM (DRAM)
(cid:139)
Memory peripheral circuit
(cid:139)
Content Addressable Memory (CAM)
(cid:139)
Serial access memories
(cid:139)
Programmable Logic Array
(cid:139)
Reliability and Yield
(cid:139)
Memory trends
(cid:139)
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 7
Memory Architecture: Decoders
M bits M bits
S
S 0
0
Word 0 Word 0
S
1
Word 1 A Word 1
0
S Storage Storage
2
Word 2 Word 2
s Cell A Cell
d 1
r
o r
W e
d
o
N c
A e
S K-1 D
N-2
Word N-2 Word N-2
S
N_1
Word N-1 Word N-1
Input-Output Input-Output
(M bits) (M bits)
N words => N select signals Decoder reduces # of select signals
Too many select signals K = log N
2
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 8
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
L-K Bit Line
2
Storage Cell
A
K
r
e Word Line
A d
K+1
o
c
e
D
A
L-1 w
o
R
K
M.2
Amplify swing to
Sense Amplifiers / Drivers
rail-to-rail amplitude
A
0
Column Decoder Selects appropriate
A word
K-1
Input-Output
(M bits)
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 9
Hierarchical Memory Architecture
Row
Address
Column
Address
Block
Address
Global Data Bus
Control Block Selector Global
Amplifier/Driver
Circuitry
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Memory and Array Circuits Introduction to Digital Integrated Circuit Design Lecture 7 - 10