Lecture 21- Multi-Step & Pipelined ADCs

31 Pages·2009·0.78 MB·English

EE247
Lecture 21
ADC Converters
–Techniques to reduce flash ADC complexity
(continued)
• Interpolating & folding (continued)
–Multi-Step ADCs
• Two-Step flash
• Pipelined ADCs
–Effect of sub-ADC, sub-DAC, gain stage non-idealities on
overall ADC performance
• Error correction by adding redundancy
• Digital calibration
• Correction for inter-stage gain nonlinearity
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 1
Parallel Folders Using Only Zero-Crossings
V
in
Folder 4 Comparator
Δ
V + 3/4 *
ref
Folder 3 Comparator
Δ LSB bits
Vref+ 2/4 * Logic
(to be combined with MSB bits)
Folder 2 Comparator
V + 1/4 * Δ
ref
Folder 1 Comparator
V + 0/4 * Δ
ref
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 2
Parallel Folder Outputs
F1
0.4 F2
F3
F4 • 4 folders with 4 folds
ut0.2 each
utp • 16 zero crossings
O
er 0 • (cid:198) 4 LSB bits
d
ol
F • Higher resolution
-0.2
• More folders
(cid:198)Large complexity
-0.4
• Interpolation
0 1 2 3 4 5
Vin /Δ
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 3
Folding & Interpolation
Folder 4
Δ
V + 3/4 *
ref
E
Folder 3 N
Fine C
Δ
Vref+ 2/4 * Flash O
ADC D
Folder 2 E
R
V + 1/4 * Δ
ref
Folder 1
V + 0/4 * Δ
ref
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 4
Folder / Interpolator Output
Example:4 Folders + 4 Resistive Interpolator per Stage
0.5
F1
ut0.4 F2
p I1
ut0.3 I2 0.04
O I3
or 0.2 0.02
at
pol0.1 0
er 0
nt -0.02
der / I--00..21 1.5 1.6 1.7 1.8
ol
F-0.3 Note: Output of two
-0.4 folders only +
corresponding
-0.5
0 1 2 3 4 5 interpolator only
Δ
Vin /
shown
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 5
A 70-MS/s 110-mW 8-b CMOS Folding
and Interpolating A/D Converter
Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 6
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
Note:
Total of 40(MSB=8, LSB=32) comparators compared to 28-1= 255for straight flash
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 7
A 70-MS/s 110-mW 8-b CMOS Folding and Interpolating A/D Converter
Ref: B. Nauta and G. Venes, JSSC Dec 1985, pp. 1302-8
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 8
Multi-Step ADCs
• Two-Step flash
• Pipelined ADCs
– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall
ADC performance
• Error correction by adding redundancy
• Digital calibration
• Correction for inter-stage gain nonlinearity
– Implementation
• Practical circuits
• Stage scaling
• Combining the bits
• Stage implementation
–Circuits
–Noise budgeting
• How many bits per stage?
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 9
Two-Step
Example: (2+2)Bits
11 V
in
ut10
2-bit ADC 2-bit ADC Do01
V
in
00
0 1 2 3
1
???
B] 0.5
S
L
+ [ 0
1
q
D = V+ ε ε -0.5
out in q1
-1
0 1 2 3
ADC Input [LSB]
• Using only one ADC: output contains large quantization error
• "Missing voltage" or "residue" ( -ε )
q1
• Idea: Use second ADC to quantize and add -ε
q1
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 10
Two Stage Example
Vref1 ε Vref2
-
V q1
in “Coarse“ - + “Fine“
2-bit ADC 2-bit DAC 2-bit ADC
ε ε
- +
q1 q2
+
ε ε ε
D = V + - +
out in q1 q1 q2
• Use DAC to compute missing voltage
• Add quantized representation of missing voltage
• Why does this help? How about ε ?
q2
• Since maximum voltage at input of the 2ndADC is V /4 then for 2ndADC
V =V /4 and thus ε = ε /4 =V /16 (cid:198)4bit overreaf1ll resolution
ref2 ref1 q2 q1 ref1
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 11
Two Step (2+2) Flash ADC
4-bit Straight Flash ADC Ideal 2-step Flash ADC
V V V
in in in
Voltage quantized
by 2ndADC
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 12
Two Stage Example
−ε
q1
11
V /22 10 V Second ADC
ref1 ref2
V V 01 “Fine“
ref1 in
00
00 01 10 11
First ADC
“Coarse“
• Fine ADC is re-used 22times
• Fine ADC's full scale range needs to span only 1 LSB of coarse
quantizer
V V
ε = ref2 = ref1
q2 22 22⋅22
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 13
Two-Stage (2+2) ADC Transfer Function
D
out
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000 V
in
V
ref1
Coarse Fine
Bits Bits
(MSB) (LSB)
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 14
Residue or Multi-Step Type ADC
Issues
er
Vin Coarse ADC DAC Fine ADC ombin B2)-Bit
(B1-Bit) (B1-Bit) Residue ((oBp2ti-oBniat)l) Bit C B1+
(
• Operation:
– Coarse ADC determines MSBs
– DAC converts the coarse ADC output to analog-Residue is found by
subtracting (V -V )
in DAC
– Fine ADC converts the residue and determines the LSBs
– Bits are combined in digital domain
• Issue:
1.Fine ADC has to have precision in the order of overall ADC 1/2LSB
2.Speed penalty (cid:198)Need at least 1 clock cycle per extra series stage to resolve
one sample
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 15
Solution to Issue (1)
Reducing Precision Required for Fine ADC
2-bit ADC 2-bit DAC ε G=2B1 2-bit ADC
-
V q1
in “Coarse“ - + “Fine“
ε ε
- +
q1 q2
+
ε ε ε
D = V + - +
out in q1 q1 q2
• Accuracy needed for fine ADC relaxed by introducing inter-stage
gain
– Example: By adding gain of x(G=2B1=4) prior to fine ADC in (2+2)bit
case, precision required for fine ADC is reduced to 2-bit only!
– Additional advantage-coarse and fine ADC can be identical stages
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 16
Solution to Issue (2)
Increasing ADC Throughput
T/H+(G=2B1)
2-bit ADC 2-bit DAC ε
-
V q1
in “Coarse“ - + “Fine“
T/H 2-bit ADC
+
ε ε ε
D = V + - +
out in q1 q1 q2
• Conversion time significantly decreased by employing T/H between
stages
– All stages busy at all times (cid:198)operation concurrent
– During one clock cycle coarse & fine ADCs operate concurrently:
• First stage samples/converts/generates residue of input signal sample # n
• While 2ndsamples/converts residue associated with sample # n-1
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 17
Multi-Step ADCs
• Two-Step flash
• Pipelined ADCs
– Effect of sub-ADC, sub-DAC, gain stage non-idealities on overall
ADC performance
• Error correction by adding redundancy
• Digital calibration
• Correction for inter-stage gain nonlinearity
– Implementation
• Practical circuits
• Stage scaling
• Combining the bits
• Stage implementation
–Circuits
–Noise budgeting
• How many bits per stage?
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 18
Pipeline ADC
Block Diagram
V V
Stage 1 res1 Stage 2 res2 Stage k
V
in B Bits B Bits B Bits
1 2 k
MSB... ...LSB
Align and Combine Data
Digital output
(B + B + ... + B) Bits
1 2 k
• Idea: Cascade several low resolution stages to obtain high overall
resolution (e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit
only!)
• Each stage performs coarse A/D conversion and computes its
quantization error, or "residue“
• All stages operate concurrently
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 19
Pipeline ADC
Characteristics
• Number of components (stages) grows linearly with
resolution
• Pipelining
– Trading latency for conversion speed
– Latency may be an issue in e.g. control systems
– Throughput limited by speed of one stage →Fast
• Versatile: 8...16bits, 1...200MS/s
• One important feature of pipeline ADC: many analog
circuit non-idealities can be corrected digitally
EECS 247-Lecture 21 Pipelined ADCs ©2009 Page 20