Lecture 18-Nyquist Rate ADCs:Track & Hold- ADC Architectures

34 Pages·2010·1.02 MB·English

by  Bernhard Boser

EE247
Lecture 18
ADC Converters
– Track & hold
• T/H circuits
• T/H combined with summing/difference function
• T/H circuit incorporating gain & offset cancellation
• T/H aperture uncertainty
– ADC architectures and design
• Serial-slope type
• Successive approximation
• Flash ADC and its sources of error: comparator offset,
sparkle code & meta-stability
– Comparator design
• Single-stage open-loop amplifier
• Cascade of open-loop amplifiers
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 1
Summary of Last Lecture
ADC Converters
– Sampling (continued)
• Sampling switch considerations
–Clock voltage boosters
• Sampling switch charge injection & clock
feedthrough
–Complementary switch
–Use of dummy device
–Bottom-plate switching
– Track & hold
• Flip around T/H
EECS 247 Lecture 17: Data Converters-ADC Design, Sampling © 2010 Page 2
Flip-Around T/H-Basic Operation
f
high
1
f
2
f
1
S2A f1D
f
1D
f
2
f f S3
1D 2 Charging C
C
v
IN v
OUT
S1A S2
Q =V xC
f1 IN
f1 S1
Note: Opamp has to be
stable in unity-gain
v configuration
CM
EECS 247 Lecture 17: Data Converters-Track & Hold-ADC Design © 2009 Page 3
Flip-Around T/H-Basic Operation
f high
2
f
2
f
1
S2A f1D
f
1D
f
2
f f S3
1D 2 Holding
C
v
IN
S1A S2 v
OUT
f1 S1
Q =V xC
f2 OUT
V = V
OUT IN
v
CM
EECS 247 Lecture 17: Data Converters-Track & Hold-ADC Design © 2009 Page 4
Differential Flip-Around T/H
S11
S12
Offset voltage associated with charge injection of S11 & S12 cancelled by differential
nature of the circuit
Ref: W. Yang, et al. “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With 85-dB SFDR at Nyquist Input,”
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001 1931
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 5
Differential Flip-Around T/H
f ’
1
f
1
f
2
•Gain=1
•Issue: Large input common-mode compliance required
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 6
Differential Flip-Around T/H
Issues: Large Input Common-Mode Compliance
1.7V
0.5V 1.2V
1V
1V
VCMVin=1.5V 1V
0.5V 0.8V
1.3V
DV =1-1.5= -0.5V
in-cm
•DV =V -V
in-cm out_com sig_com
Drawback: Amplifier needs to have large input common-mode
compliance
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 7
Input Common-Mode
Cancellation
•Note: Shorting switch M3 added
Ref: R. Yen, et al. “A MOS Switched-Capacitor Instrumentation Amplifier,” IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VOL. SC-17, NO. 6,, DECEMBER 1982 1008
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 8
Input Common-Mode Cancellation
+ 1.2 - + 0.1 -
1V+0.2V
+
0.1
-
-0.1 +
1V-0.2V -
+ 0.8 - 0.1
+
Track mode (fhigh) Hold mode (flow)
VC1=VI1 , VC2=VI2 Vo1+Vo2 =0
Vo1=Vo2=0 Vo1-Vo2= -(VI1-VI2)(C1/(C1+C3))
Input common-mode level removed
•Will introduce active version in page 18
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 9
Switched-Capacitor Techniques Combining
Track & Hold with Various other Functions
• T/H + Charge redistribution amplifier
• T/H & Input difference amplifier
• T/H & summing amplifier
• Differential T/H combined with gain stage
• Differential T/H including offset cancellation
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 10
T/H + Charge Redistribution Amplifier
Track mode: (S1, S3 on S2 off)
V =V –V , V =0
C1 os IN C2
V=V
o os
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 11
T/H + Charge Redistribution Amplifier
Hold Mode
22
1
Hold/amplify mode (S1, S3 off S2on)
Offset NOT cancelled, but not amplified
Input-referred offset =(C /C ) x V , & often C <C
2 1 OS 2 1
Can incorporate gain by having C >C
1 2
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 12
T/H & Input Difference Amplifier
Sample mode:
(S1, S3 on S2off)
V =V –V , V =0
C1 os I1 C2
V=V
o os
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 13
Input Difference Amplifier
Cont„d
Subtract/Amplify mode (S1, S3 off S2on)
During previous phase:
V =V –V , V =0
C1 os I1 C2
V=V
o os
1
Offset NOT cancelled, but not amplified
Input-referred offset =(C /C )xV , & C <C
2 1 OS 2 1
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 14
T/H & Summing Amplifier
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 15
T/H & Summing Amplifier
Cont„d
Sample mode (S1, S3, S5on S2, S4off)
V =V –V , V =V -V , V =0
C1 os I1 C2 os I3 C3
V=V
o os
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 16
T/H & Summing Amplifier
Cont„d
Amplify mode (S1, S3, S5off, S2, S4on)
3
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 17
Differential T/H Combined with Gain Stage
Employs the previously discussed technique to eliminate the problem associated
with high common-mode voltage excursion at the input of the opamp
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE
JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 18
Differential T/H Combined with Gain Stage
f1  High
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE
JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 19
Differential T/H Combined with Gain Stage
• Gain=4C/C=4
• Input voltage common-mode level removed opamp can have low input
common-mode compliance
• Amplifier offset NOT removed
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE
JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
EECS 247 Lecture 18: Data Converters-Track & Hold-ADC Design © 2010 Page 20