Learning from VLSI Design Experience PDF
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Weng Fook Lee Learning from VLSI Design Experience Learning from VLSI Design Experience Weng Fook Lee Learning from VLSI Design Experience Weng Fook Lee Emerald Systems Bayan Lepas, Malaysia ISBN 978-3-030-03237-1 ISBN 978-3-030-03238-8 (eBook) https://doi.org/10.1007/978-3-030-03238-8 Library of Congress Control Number: 2018960261 © Springer Nature Switzerland AG 2019 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland Dedicated to my kids, my most treasured gift. Preface Digital systems are widely used in our daily lives. From household appliances to mobile smartphone and tablets, digital IC (integrated circuits) chips form a large part of our lives, whether we can clearly identify the presence of these IC chips in the systems we use. As technology becomes a bigger part of our lives, these IC chips increase in complexity from a few thousand transistors (Intel’s 4004 in 1971) to 3.3 billion transistors (Apple’s A10 Fusion in 2016). More and more functionalities are cramped into a single IC chip increasing its complexity. It is common to find IC chips with few million transistors and more. Such complexity increases the diffi- culty level for IC designers to design the circuitry for the IC chips. Digital design methodology and flow are used with Hardware Description Language such as Verilog to aid the designer to design these complex circuitries. Chapter 1 is an introduction to digital systems, while Chap. 2 discusses about analog/custom design flow and digital design flow. Technical details on each step of the flow are discussed from RTL (Register-Transfer Level) coding through simula- tion, synthesis, auto place and route to final tapeout. Chapter 2 covers details on the cells in a standard cell library. Standard cell library plays an important role in synthesis as the synthesis process synthesizes RTL code into logic gates using the available logic gates from the standard cell library. Logic cells commonly found in standard cell library are discussed with schematics on the standard cell’s structure. Design constraints such as input delay, output delay, multicycle path, and false path are discussed in Chap. 2. Clock tree synthesis which plays an important role in physical backend auto place and route is described in this chapter, describing how clock skew occurs between different clock paths. Floorplan of physical backend prior to clock tree synthesis is also discussed in Chap. 2. Chapter 3 describes in detail on clock domain crossing for multi-asynchronous clocks in a design. Calculation of mean time and explanations using synchronizers in extending the mean time between failures for clock domain crossing are described. The conditions of using synchronizer to fix clock domain crossing for faster trans- mit clock compared to receiving clock and vice versa are discussed in detail in Chap. 3. vii viii Preface Differences between synchronous reset and asynchronous reset are also dis- cussed in Chap. 3 with examples of correct RTL coding for these reset conditions. Latch inference is undesirable in logic design and should be avoided. Chapter 4 discusses RTL coding conditions that lead to latch inference in a design. Examples of if-else statements and case statements that lead to latch inference are described in this chapter. With majority of ASIC and SOC design being multimillion gates, testability of design becomes a critical issue. Chapter 5 discusses about scan chain and ATPG and how it can be used for testability. There are examples in Chap. 5 showing how a scan insertion occurs in a design with the scan flops being stitched to form scan chain. Test compression is also discussed in Chap. 5 on handling multiple scan chains for large design. For large design with multiple asynchronous clocks, Chap. 5 discusses on han- dling of scan chain design when crossing clock domain. Capture cycle of ATPG involving multiple clocks is also covered in Chap. 5. Apart from scan chain and ATPG, Chap. 5 also covers logic BIST and memory BIST and how it is used in ASIC and SOC. Signed Verilog is important for design that requires computation for positive and negative, for example, field-oriented control logic for controlling of motor move- ments for complex motor such as Brushless Direct Current (BLDC) motor and Permanent Magnet Synchronous Motor (PMSM). Chapter 6 discusses in detail the usage of signed and unsigned, with descriptions of the consequences of mixing signed and unsigned in the RTL. State machines are commonly found in ASIC and SOC design. Chapter 7 shows the different state machine encoding and RTL coding styles for designing state machine. Blocking statements and non-blocking statements commonly found in proce- dural statements are also discussed in detail in Chap. 7. Chapter 8 discusses common RTL coding guidelines that designers can follow to ensure good RTL code. Complete sensitivity list, edge-triggered RTL, level- triggered RTL, handling of bidirectional ports in RTL, when to use blocking state- ment and when to use non-blocking statement, inferred latch, signed Verilog, logic between modules, registering output of modules, and naming convention are dis- cussed in detail in Chap. 8. With today’s complex large ASIC and SOC, it is important to ensure the RTL is well covered and verified with the testbenches. Code coverage is a method to mea- sure the percentage of RTL code coverage by the corresponding testbenches. RTL code that are not exercised by the testbenches are identified by code coverage. Chapter 9 discusses about code coverage and shows the different types of code cov- erage. Chapter 9 also shows how designers can use the information obtained from code coverage reports to enhance the testbenches to cover the missing coverage. All the chapters in this book consist of many pictures and diagrams to help the reader visualize and understand the design examples. Many examples are provided throughout the book to help assist the reader to understand the complications and issues presented and solutions to overcome them. Preface ix This book’s target audience are students learning VLSI design and young design engineers learning the art of VLSI design. This book explains design from a practi- cal perspective based on years of design knowledge gained from experience. Bayan Lepas, Malaysia Weng Fook Lee Trademarks Pyxis, Calibre, Kronos, Modelsim, Leonardo Spectrum, DFT Advisor, Fastscan, Testkompress, Logic BIST, MBISTArchitect, and HDL Designer are trademarks of Mentor Graphics Inc. Composer is a trademark of Cadence Inc. Cyclone and Aria are trademarks of Altera/Intel Corp. xi Acknowledgment This book would not have been possible without the help of many people. I would like to put forward a word of “Thank You” to my wife for her companionship; I am looking forward to many more years of companionship on this journey of life; to my kids, for sitting with me at the study table while I write this book and they work on their school assignments; and to my besties, LP, SC, and BH, thank you for your patience in listening to my endless stories and for always being there for me. xiii
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