Layout Optimization in VLSI Design

292 Pages·2001·15.962 MB·English

by  Hung-Ming Chen, Martin D. F. Wong, Hai Zhou (auth.), Bing Lu, Ding-Zhu Du, Sachin S. Sapatnekar (eds.)

Layout Optimization in VLSI Design
Network Theory and Applications
Volume 8
Managing Editors:
Ding-Zhu Du, University ofM innesota, U.S.A.
and
Cauligi Raghavendra, University of Southern California, U.S.A.
Layout Optimization in
VLSI Design
Edited by
Bing Lu and Ding-Zhu Du
Department of Computer Science and Engineering,
University ofM innesota, Minneapolis, MN, U.s.A.
and
Sachin S. Sapatnekar
Department of Electrical and Computer Engineering,
University of Minnesota, Minneapolis, MN, U.S.A.
SPRINGER-SCIENCE+BUSINESS MEDIA, B.V.
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-5206-6 ISBN 978-1-4757-3415-7 (eBook)
DOI 10.1007/978-1-4757-3415-7
Printed on acid-free paper
All Rights Reserved
© 2001 Springer Science+Business Media Dordrecht
Originally published by Kluwer Academic Publishers in 2001
Softcover reprint of the hardcover 1st edition 2001
No part of the material protected by this copyright notice may be reproduced or
utilized in any form or by any means, electronic or mechanical,
including photocopying, recording or by any information storage and
retrieval system, without written permission from the copyright owner.
Contents
Preface ............................. vii
1. Integrated Floorplanning and Interconnect Planning .. 1
H.-M. Chen. Martin D.F. Wong, H. Zhou, F. Y. Young, H. H. Yang,
and N. Sherwani
2. Interconnect Planning ................... 19
J. Cong
3. Modern Standard-cell Placement Techniques ...... 45
X. Yang, E. Bozorgzadeh, M. SarraJzadeh, and M. Wang
4. Non-Hanan Optimization for Global VLSI Interconnect 89
J. Hu and S. S. Sapatnekar
5. Techniques for Timing-Driven Routing ......... 125
J. Lillis
6. Interconnect Modeling and Design with Consideration
of Inductance "" .. " .. " " .. ," ............ 155
1. He
7. Modeling and Characterization of IC Interconnects
and Packagings for the Signal Intergrity Verification on
High-Performance VLSI Circuits .............. 191
Y. Eo
8. Tradeoffs in Digital Binary Adder Design: the Effects
of Floorplanning, Number of Levels of Metals, and Supply
Voltage on Performance and Area .... " .... " .... 261
V. Kantabutra, S. Perri, and P. Corsonello
v
Preface
Introduction
The exponential scaling of feature sizes in semiconductor technologies
has side-effects on layout optimization, related to effects such as inter
connect delay, noise and crosstalk, signal integrity, parasitics effects, and
power dissipation, that invalidate the assumptions that form the basis
of previous design methodologies and tools. This book is intended to
sample the most important, contemporary, and advanced layout opti
mization problems emerging with the advent of very deep submicron
technologies in semiconductor processing. We hope that it will stimulate
more people to perform research that leads to advances in the design
and development of more efficient, effective, and elegant algorithms and
design tools.
Organization of the Book
The book is organized as follows. A multi-stage simulated annealing
algorithm that integrates floorplanning and interconnect planning is pre
sented in Chapter 1. To reduce the run time, different interconnect plan
ning approaches are applied in different ranges of temperatures. Chapter
2 introduces a new design methodology - the interconnect-centric design
methodology and its centerpiece, interconnect planning, which consists of
physical hierarchy generation, floorplanning with interconnect planning,
and interconnect architecture planning. Chapter 3 investigates a net-cut
minimization based placement tool, Dragon, which integrates the state
of the art partitioning and placement techniques.
Chapter 4 deals with the single-net global routing tree optimization
problem under stringent timing constraints. It is shown that the use
of non-Hanan Steiner nodes is necessary for the maximum sink delay
minimization problem and the specified delay achievement problem, and
techniques for solving these problems are developed. Chapter 5 turns
to techniques for combining routing and delay optimization for two pin
nets. Basic timing-driven maze routing, simultaneous routing and basic
vii
Preface
Vlll
timing-driven maze routing, and buffer insertion algorithms are described
in this chapter. An efficient approach for table-based inductance extrac
tion and its applications are described in Chapter 6. In addition, the
chapter develops a formulation and an algorithm for simultaneous shield
insertion and net ordering problem for interconnect synthesis of multiple
RLC nets.
As IC interconnects become narrower and are integrated in tighter
physical configurations, more accurate characterization and modeling of
the interconnect and package is demanded. Chapter 7 outlines methods
for accurately characterizing and modeling the interconnect, signal delay,
crosstalk noise, and simultaneous switching noise.
Chapter 8 presents a set of experimental results which show the ef
fects of floorplanning, number of levels of metals, and supply voltage
on areald elay requirement in digital binary adders designs. This case
study emphasizes the importance of global floorplanning and highlights
the need of new floorplanning algorithms which consider the above pa
rameters.
To the Professional
The wide and advanced topics in this book make it an excellent hand
book for researchers on VLSI CAD designs, heuristic algorithms, and
approximation algorithms. Each chapter is relatively self-contained, and
you may focus on topics that are of the greatest interest. You will also
find the extensive bibliography useful to find advanced material on a
topic.
Acknowledgements
We are grateful to all our colleagues and friends who have contributed
greatly to the quality of this book. We would like to thank all of you for
your useful suggestions and constructive criticisms. Finally, we would
also like to thank reviewers and authors of each chapter for their contin
ued support and their work on this book.
Minneapolis, Minnesota Bing Lu
U.S.A. Ding-Zhu Du
April, 2001 Sachin S. Sapatnekar
Integrated Floorplanning and Interconnect
Planning
Hung-Ming Chen
Department of Computer Sciences
The University of Texas at Austin, Austin, TX 78712
E-mail: hmchen@cs. utexas. edu
Martin D.F. Wong
Department of Computer Sciences
The University of Texas at Austin, Austin, TX 78712
E-mail: wong@cs. utexas. edu
Hai Zhou
Advanced Technology Group
Synopsys, Inc. Mountain View, CA 94043
E-mail: [email protected]
Fung-Yu Young
Department of Computer Science and Engineering
The Chinese Umversity of Hong Kong, Shatin, Hong Kong
E-mail: [email protected]
Hannah H. Yang
Strategic CAD Labs
Intel Corporation, Hillsboro, OR 97124
E-mail: [email protected]
N aveed Sherwani
Strategic CAD Labs
Intel Corporation, Hillsboro, OR 97124
E-mail: [email protected]
B. Lu et al. (eds.), Layout Optimization in VLSI Design, 1-18.
© 2001 Kluwer Academic Publishers.
2 H.-M. Chen et al.
Contents
Abstract 2
1 Introduction 2
2 Efficient Interconnect Planning 5
2.1 Pin Assignment . . . . . . . . . . . . . . 5
2.2 Simple-Geometry Routing . . . . . . . . 6
2.3 Incremental Routing Cost Computation 8
3 Multi-Stage Simulated Annealing 10
3.1 Cost Function Transitions 11
3.2 Temperature Adjustment 12
4 Experimental Results 15
5 Conclusion 15
6 Acknowledgements 16
References
Abstract
When VLSI technology enters the deep sub-micron era, communi
cation between different components is significantly increased. Inter
connect delay also becomes the dominant factor in total circuit delay.
All these make it necessary to start interconect planning as early as
possible. In this chapter, we propose a method to combine interconnect
planning with floorplanning. Our approach is based on the Wong-Liu
floorplanning algorithm. When the positions, orientations, and shapes
of the cells are decided, the pin positions and routing of the intercon
nects are decided as well. We use a multi-stage simulated annealing
approach in which different interconnect planning methods are used
in different ranges of temperatures to reduce running time. A tem
perature adjustment scheme is designed to give smooth transistions
between different stages of simulated annealing. Experimental results
show that our approach performs well,
1 Introd uction
With VLSI technology entering the deep sub-micron (DSM) era, devices
are scaled down to smaller sizes and placed at an ever increasing proximity.