Inverter-based Circuit Design Techniques for Low Supply Voltages

134 Pages·2017·3.178 MB·english

by  Rakesh Kumar Palani, Ramesh Harjani

Rakesh Kumar Palani • Ramesh Harjani
Inverter-based Circuit
Design Techniques
for Low Supply Voltages
123
RakeshKumarPalani RameshHarjani
DepartmentofElectrical DepartmentofElectrical
andComputerEngineering andComputerEngineering
UniversityofMinnesota UniversityofMinnesota
Minneapolis,MN,USA Minneapolis,MN,USA
ISSN1872-082X ISSN2197-1854 (electronic)
AnalogCircuitsandSignalProcessing
ISBN978-3-319-46626-2 ISBN978-3-319-46628-6 (eBook)
DOI10.1007/978-3-319-46628-6
LibraryofCongressControlNumber:2016952245
©SpringerInternationalPublishingAG2017
ThisSpringerimprintispublishedbySpringerNature
TheregisteredcompanyisSpringerInternationalPublishingAG
Theregisteredcompanyaddressis:Gewerbestrasse11,6330Cham,Switzerland
Preface
Rapid advances in the field of integrated circuit design has been advantageous
fromthepointofviewofcostandminiaturization.Althoughtechnologyscalingis
advantageoustodigitalcircuitsintermsofincreasedspeedandlowerpower,analog
circuitsstronglysufferfromthistrend.Thisisbecomingacrucialbottleneckinthe
realization of a system on chip in scaled technology merging high-density digital
partswithhigh-performanceanaloginterfaces.Thisisbecausescaledtechnologies
reduce the output impedance (gain) and supply voltage which limits the dynamic
range(outputswing).Onewaytomitigatethepowersupplyrestrictionsistomove
tocurrentmodecircuitdesignratherthanvoltagemodedesigns.
This thesis focuses on designing process, voltage, and temperature (PVT)-
tolerant base band circuits at lower supply voltages and in lower technologies.
Inverter amplifiers are known to have better transconductance efficiency, better
noise, and linearity performance. But inverters are prone to PVT variations and
havepoorCMRRandPSRR.Tocircumventtheproblem,wehaveproposedvarious
biasing schemes for inverters like semi-constant current biasing, constant current
biasing, and constantgm biasing. Each biasing technique has its own advantages,
like semi-constant current biasing allows to select different PMOS and NMOS
current.Thisfeatureallowforhigherinherentinverterlinearity.Similarlyconstant
currentand constantgm biasing allows for reducedPVT sensitivity. The inverter-
based OTA achieves a measured THD of (cid:2)90:6dB, SNR of 78.7dB, CMRR of
97dB, and PSRR of 61dB while operating from a nominal power of 0.9V and
at output swing of 0.9Vpp;diff in TSMC 40nm general purpose process. Further,
themeasuredthirdharmonicdistortionvariesapproximatelyby11.5dBwith120ı
variationintemperatureand9dBwithan18%variationinsupplyvoltage.
The linearity can be increased by increasing the loop gain and bandwidth in
a negative feedback circuit or by increasing the over drive voltage in open loop
architectures. However both these techniques increases the noise contribution of
the circuit. There exist a trade off between noise and linearity in analog circuits.
Tocircumventthisproblem,wehaveintroducednonlinearcancellationtechniques
andnoisefilteringtechniques.Ananalog-to-digitalconverter(ADC)driverwhichis
capableofamplifyingthecontinuoustimesignalwithagainof8andsampleonto
theinputcapacitor(1pF)of110bitsuccessiveapproximationregister(SAR)ADC
isdesignedinTSMC65nmgeneralpurposeprocess.Thisexploitsthenon-linearity
cancellation in current mirror and also allows for higher bandwidth operation by
decouplingclosed loop gain from the negativefeedbackloop. The noise from the
outofbandisfilteredbeforesamplingleadingtolownoiseoperation.Themeasured
designoperatesat100MS/sandhpasanOIP3 of40dBm attheNyquistrate,noise
power spectral density of 17nV/ Hz, and inter-modulation distortion of 65dB.
The intermodulation distortion variation across ten chips is 6 and 4dB across a
temperaturevariationof120ıC.
Non-linearitycancellationisexploitedindesigningtwofilters,ananti-aliasfilter
and a continuously tunable channel select filter. Traditional active RC filters are
based on cascade of integrators. These create multiple low impedance nodes in
thecircuitwhichresultsin a highernoise.We proposea reallow passfilter-based
filterarchitectureratherthanthetraditionalintegrator-basedapproach.Further,the
entire filtering operation takes place in current domain to circumvent the power
supply limitations. This also facilitates the use of tunable non-linear metal oxide
semiconductorcapacitor(MOSCAP)asfiltercapacitors.Weintroducetechniquesof
self-compensationtousethefilterresistorandcapacitorascompensationcapacitor
for lower power. The anti-alias filter designed for 50MHz bandwidth that is
fabricated in IBM 65nm process achieves an IIP3 of 33dBm while consuming
1.56mWfrom1.2Vsupply.Thechannelselectfilteristunablefrom34to314MHz
and is fabricated in TSMC 65nm general purpose process. This filter achieves
an OIP3 of 25.24dBm at the maximum frequency while drawing 4.2mA from
1.1Vsupply.Themeasuredintermodulationdistortionvariesby5dBacross120ıC
variation in temperature and 6.5dB across a 200mV variation in power supply.
Further,thisfilterpresentsahighimpedancenodeattheinputandalowimpedance
nodeattheoutputeasingsystemintegration.
SAR ADCs are becoming popular at lower technologies as they are based on
device switching rather than amplifyingcircuits. But recentSAR ADCs that have
good energy efficiency have had relatively large input capacitance increasing the
driverpower.Wepresenta2Xtimeinterleaved(TI)SARADCwhichhasthelowest
inputcapacitanceof133fFinliterature.Thesamplingcapacitorisseparatedfrom
thecapacitivedigitaltoanalogconverter(DAC)arraybyperformingtheinputand
DACreferencesubtractioninthecurrentdomainratherthanasdonetraditionallyin
chargedomain.TheproposedADCisfabricatedinTSMC’s65nmgeneralpurpose
process and occupies an area of 0.0338mm2. The measured ADC spurious free
dynamicrange(SFDR)is57dB,andthemeasuredeffectivenumberofbits(ENOB)
atNyquistrateis7.55bitwhileusing1.55mWpowerfrom1Vsupply.
Minneapolis,MN,USA RakeshKumarPalani
RameshHarjani
Contents
1 Introduction .................................................................. 1
1.1 TraditionalOperationalTransconductance ............................ 4
1.2 DifferentialPairVersusInverter........................................ 7
1.3 NonLinearityAnalysis................................................. 9
1.4 NoiseAnalysis .......................................................... 10
1.5 InverterTransconductor................................................. 11
1.6 Non-linearityCancellationTechniques................................ 13
1.7 Organization............................................................. 14
2 Biasing ........................................................................ 17
2.1 Semi-constantCurrentBiasing......................................... 17
2.1.1 OptimalNMOS-PMOSRatioing .............................. 19
2.1.2 NonLinearityCancellationinInverters ....................... 20
2.1.3 Case1:SmallInput............................................. 21
2.1.4 Case2:LargeInput............................................. 22
2.1.5 Simulation....................................................... 23
2.2 ConstantCurrentBiasing............................................... 23
2.3 Constant-gmBiasing.................................................... 25
2.4 Conclusion .............................................................. 27
3 InverterBasedOTADesign ................................................ 29
3.1 OTADesign ............................................................. 30
3.1.1 CommonModeRejectionStage ............................... 31
3.1.2 GainandDriverStage.......................................... 32
3.2 MeasurementResults ................................................... 34
3.3 Conclusion .............................................................. 39
4 ADCDriver .................................................................. 41
4.1 ADCDriver ............................................................. 42
4.2 OTADrivingLoad...................................................... 42
4.2.1 DrivingLoadCapacitorDirectly............................... 42
4.2.2 DrivingLoadCapacitorThroughResistor .................... 43
4.3 ContinuousandDiscreteTimeADCDriver........................... 46
4.3.1 ContinuousTimeDriver........................................ 46
4.3.2 DiscreteTimeDriver ........................................... 48
4.4 SimulationtoVerifyNoiseFiltering................................... 49
4.5 ADCDriverArchitecture............................................... 51
4.6 ComponentsoftheADCDriver........................................ 52
4.6.1 CurrentMirrorDesign.......................................... 52
4.6.2 Trans-ImpedanceAmplifier(TIA)Design .................... 54
4.6.3 Anti-AliasFilter ................................................ 56
4.6.4 Sampler.......................................................... 56
4.6.5 PassiveAmplification........................................... 57
4.7 Measurements........................................................... 57
4.8 Conclusion .............................................................. 61
5 CurrentMirrorBasedFilter ............................................... 63
5.1 IntegratorDesign........................................................ 65
5.1.1 Non-LinearityCancellation .................................... 67
5.1.2 BandwidthLimitationEffects.................................. 69
5.1.3 GainLimitationEffects......................................... 70
5.1.4 NoiseAnalysis.................................................. 71
5.2 FilterDesign............................................................. 72
5.2.1 Current-DomainBiquad........................................ 72
5.2.2 EffectofOTANonidealitiesonBiquad ....................... 73
5.2.3 ButterworthFilterDesign ...................................... 74
5.2.4 CompensationoftheAmplifiers............................... 75
5.2.5 NoiseComparisonwithActiveRCIntegratorFilter.......... 78
5.3 Measurements........................................................... 82
5.4 Conclusion .............................................................. 85
6 AllMOSCAPBasedContinuouslyTunableFilter ....................... 87
6.1 FilterArchitecture....................................................... 88
6.1.1 RootLocus...................................................... 88
6.1.2 First-OrderSystem.............................................. 90
6.1.3 ThirdOrderFilter............................................... 95
6.2 BiasingandCMFB...................................................... 95
6.3 MeasurementResults ................................................... 96
6.4 Conclusion .............................................................. 100
7 ADC ........................................................................... 103
7.1 ADCArchitecture....................................................... 106
7.2 DACDesign............................................................. 107
7.3 SamplerDesign ......................................................... 108
7.4 PreampDesign.......................................................... 108
7.4.1 InputVoltageRange............................................ 110
7.4.2 PreampTransconductanceLinearity........................... 111
7.4.3 InputCapacitanceLinearity.................................... 113
7.4.4 GateLeakage.................................................... 113
7.5 MeasurementResults ................................................... 114
7.6 Conclusion .............................................................. 120
References......................................................................... 123
Figures
Fig.1.1 ITRSroadmap ........................................................ 2
Fig.1.2 Developmentinmobileindustry .................................... 2
Fig.1.3 TypicalRFreceiver .................................................. 3
Fig.1.4 Analogdesignoctagon ............................................... 3
Fig.1.5 Fivetransistordifferentialpair ...................................... 4
Fig.1.6 TelescopicfoldedOTA ............................................... 5
Fig.1.7 FoldedcascodeOTA ................................................. 5
Fig.1.8 CurrentmirrorOTA .................................................. 6
Fig.1.9 TwostagetelescopiccascodedOTA ................................ 6
Fig.1.10 Inputandoutputswingsof(a)differentialpairand
(b)inverterOTAs ..................................................... 8
Fig.1.11 Output current of a differential pair and
pseudo-differentialinverter .......................................... 10
Fig.1.12 Outputimpedancevariationwith outputswing in
differentialpairandinverter ......................................... 10
Fig.1.13 Nautainvertertransconductor ....................................... 11
Fig.1.14 Inverterbased2stageOTA .......................................... 12
Fig.1.15 Traditionalnon-linearitycancellationtechniques .................. 14
Fig.2.1 Circuitschematicforsemi-constantcurrentinverter
biasing ................................................................ 18
Fig.2.2 Biasingnetworkcurrentwithpowersupplyvariation .............. 18
Fig.2.3 Variationofinvertertransconductancewithtemperature
andsupply ............................................................ 19
Fig.2.4 Variationofinvertertransconductanceswithpower
supplyacrossprocesscornerfortraditionalreplica
biasedinvertersandSCCBinverters ................................ 20
Fig.2.5 Circuitschematic forconstantcurrentbiasingfor
inverters ............................................................... 23
Fig.2.6 Variationofconstantcurrentbiasedinvertergmwith
powersupplyacrossprocesscornersat27ıCandwith
temperatureintypicalcorner ........................................ 24
Fig.2.7 Choice of bias currentbased on intermodulation
distortion ............................................................. 24
Fig.2.8 Circuitschematicforconstantgmbiasingforinverters ............ 25
Fig.2.9 Variation of constant gm biased inverter
transconductancewithpowersupplyacrossprocess
corners ................................................................ 26
Fig.2.10 MonteCarlosimulationforaconstantgminverter................. 27
Fig.3.1 BlockdiagramoftheproposedinverterbasedOTA ................ 31
Fig.3.2 CircuitschematicofCMRSstage ................................... 31
Fig.3.3 Simulated CMRS gainwith inputcommonmode
voltage ................................................................ 32
Fig.3.4 Circuitschematicofgainanddriverstage .......................... 33
Fig.3.5 Simulateddrivergainwithoutputswing ............................ 33
Fig.3.6 Biasingoftransistorsingainstage .................................. 34
Fig.3.7 MicrographofproposedOTA ....................................... 35
Fig.3.8 TestsetupoftheOTA ................................................ 35
Fig.3.9 MeasuredmagnituderesponseoftheOTA ......................... 36
Fig.3.10 MeasuredslewrateoftheOTA ...................................... 37
Fig.3.11 Measuredcommonmoderejectionratio(CMRR)and
powersupplyrejectionratio(PSRR)ofOTA ....................... 37
Fig.3.12 ScreenshotofsingleendedmeasuredspectrumofOTA
outputat9.5MHz900mV ...................................... 38
ppdiff
Fig.3.13 Measuredthirdorderdistortionversusfrequencyover
temperature ........................................................... 38
Fig.3.14 Measuredthirdorderdistortionversusfrequencyover
powersupply ......................................................... 39
Fig.4.1 ADCdriver ........................................................... 43
Fig.4.2 LoopgainoftheADCdriver ........................................ 43
Fig.4.3 ADCdriver ........................................................... 44
Fig.4.4 LoopgainoftheADCdriverwhiledrivingcapacitive
loadthroughresistor ................................................. 44
Fig.4.5 BodeplotofloopgainofADCdriver .............................. 45
Fig.4.6 ContinuoustimeADCdriver ........................................ 47
Fig.4.7 DiscretetimeADCdriver ............................................ 48
Fig.4.8 Simulation test bench to verify noise filtering.
(a)Withoutresistor;(b)Withresistor................................ 50
Fig.4.9 Outputnoisepowerspectraldensitywithandwithout
seriesresistorR ...................................................... 50
f
Fig.4.10 Cumulativenoiseintegralwithandwithoutseries
resistorR ............................................................. 51
f
Fig.4.11 Blockdiagramoftherail-to-railoutputsampledADC
driver .................................................................. 51
Fig.4.12 CircuitschematicfortheADCdriver ............................... 52
Fig.4.13 Simulationofthevoltagetocurrentconvertercircuit
overdifferentclosedloopgain ...................................... 53
Fig.4.14 CircuitschematicfortheOTAs ...................................... 55
Fig.4.15 Comparisonofinverting(a)andtransimpedance(b)amplifiers.... 55
Fig.4.16 MicrographoftheADCdriver ...................................... 58
Fig.4.17 MagnituderesponseoftheADCdriver ............................. 58
Fig.4.18 MeasuredIIP3at50MHzusingtwotoneswith1MHz
offset .................................................................. 58
Fig.4.19 MeasuredIMDfor2V outputwith1MHztones
pp-diff
separation.Red,blueandgreenlinesindicatethree
differentchips ........................................................ 59
Fig.4.20 MeasuredIMDfor2V outputwith1MHztones
pp-diff
separationatdifferenttemperatures ................................. 59
Fig.4.21 MeasuredIMDwithtonesat50MHzseparatedby
1MHzacrosschips .................................................. 60
Fig.4.22 MeasuredIMDwithtonesat50MHzseparatedby
1MHz ................................................................. 60
Fig.4.23 SimulatedMonteCarloanalysisonIMD ........................... 61
Fig.4.24 Screencaptureofthenoisemeasurement ........................... 61
Fig.5.1 PassiveRClowpasscircuit(a)anditsfeedbackmodel(b) ........ 64
Fig.5.2 ActiveRCintegrator ................................................. 64
Fig.5.3 PolesinanactiveRCfilter.(a)Conventionalbiquad
poles;(b)proposedbiquadpoles..................................... 65
Fig.5.4 A conventionalactive-RC integrator(a) and the
proposedintegrator(b) ............................................... 66
Fig.5.5 AconventionalG -Cintegrator(a)andafunctional
m
diagramoftheproposeddesignwhichlinearizesits
G -Coutputsection(b).............................................. 66
m
Fig.5.6 Non-linearcancellationinproposedintegrator ..................... 68
Fig.5.7 MonteCarlosimulationonthecurrentmirror ...................... 69
Fig.5.8 Noisesourcesintheproposedintegrator ........................... 71
Fig.5.9 Currentmodelowpassfilterbasedbiquad ......................... 72
Fig.5.10 EffectofOTAnon-idealitiesonbiquad ............................. 74
Fig.5.11 Schematicofthethirdorderfilterusingtheproposed
integratorandcurrent-modebiquad ................................. 75
Fig.5.12 Compensationofnegativefeedbackloopsinbiquad
usingfiltercomponents .............................................. 76
Fig.5.13 Schematicofloopgainofonestageinbiquad ..................... 76
Fig.5.14 MonteCarlosimulationonanegativefeedbackloopin
biquad ................................................................. 78
Fig.5.15 Cornersimulationonanegativefeedbackloopinbiquad.......... 78