Introduction to IDDQ Testing

335 Pages·1997·21.351 MB·English

by  Sreejit Chakravarty, Paul J. Thadikaran (auth.)

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FRONTIERS IN ELECTRONIC TESTING
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Vishwani D. Agrawal
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INTRODUCTION TO
I TESTING
DDQ
by
Sreejit Chakravarty
State University of New York at Buffalo
and
Paul J. Thadikaran
Intel Corporation
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication
Introduction to IDDQ Testing
by Sreejit Chakravarty and Paul J. Thadikaran
ISBN 978-1-4613-7812-9 ISBN 978-1-4615-6137-8 (eBook)
DOI 10.1007/978-1-4615-6137-8
Copyright <ro 1997 Springer Science+Business Media New York. Second Printing 2002.
Originally published by Kluwer Academic Publishers in 1997
Softcover reprint of the hardcover 1s t edition 1997
This printing is a digital duplication of the original edition.
AII rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher, with the exception of
any material supplied specificaIly for the purpose of being entered and executed on a
computer system, for exclusive use by the purchaser of the work.
Printed on acid-free pap er.
To the loving memory of my father (Prof. Sunil Chakrabarti), my mother
(Maya), Kohinoor and Ayush for their love and understanding.
sc
To my father (T. P. Joseph), mother (Mary) and Lini for support and encour
agement.
PJT
CONTENTS
FOREWORD xi
PREFACE xv
1 INTRODUCTION 1
1.1 What is IDDQ Testing? 1
1.2 Why IDDQ Testing? 4
1.3 Outline ofthe Book 6
2 WHY IDDQ TESTING? 9
2.1 Dollars and Cents 10
2.2 Area, Coverage and Quality 15
2.3 Empirical Data on Quality 16
2.4 Empirical Data on Reliability 20
2.5 IDDQ and High Voltage Stress Screens 24
3 PUTTING IDDQ TESTING TO WORK 27
3.1 IDDQ Threshold 28
3.2 IDDQ Testing ofDeep Submicron Devices 36
3.3 Current Signature 39
3.4 Speed and Number of IDDQ Measurements 42
3.5 IDDQ Testing Related Design Issues 45
3.6 Summary 58
4 PHYSICAL DEFECTS 59
4.1 Gate-Oxide Shorts 60
4.2 Shorts 63
vii
viii INTRODUCTION TO IDDQ TESTING
4.3 Opens 70
4.4 Anomalies in Detecting Bridges Using IDDQ 77
4.5 IDDQ DFT for flip-flops and scan-chains 82
4.6 IDDQ Testing ofRAMs 91
4.7 Summary 97
5 TEST SUITES, FAULT MODELS, TEST SETS
AND DEFECTS 99
5.1 Test Suites 100
5.2 Fault Models for Slow Speed Testing 102
5.3 Fault Models for High Speed Testing 106
5.4 Fault Models for IDDQ Testing 114
5.5 Defects and Fault Models 132
6 EVALUATING I TESTS 145
DDQ
6.1 Simulation ofExtracted BFs 145
6.2 Simulation ofMetal BFs and All BFs 147
6.3 Simulation ofLeakage Faults 169
6.4 Simulation ofWeak Faults 171
6.5 Summary 172
7 SELECTING I TESTS 175
DDQ
7.1 Every Vector Method 176
7.2 IDDQ Test Selection 177
7.3 Selecting IDDQ Tests for Extracted BFs 181
7.4 Selecting IDDQ Tests for Leakage and Weak Faults 184
7.5 Selecting IDDQ Tests for Metal BF and All BF 187
7.6 Summary 198
8 COMPUTING I TESTS 201
DDQ
8.1 Fault Collapsing 201
8.2 TC..ATPG for Combinational Circuits 207
8.3 CURRENT for Extracted BFs 212
8.4 ATPG for Leakage and Metal BFs using CUTEGEN 217
8.5 Analysis ofATPG for Combinational Circuits 217
8.6 ATPG for Sequential Circuits 225
Contents ix
8.7 Summary 226
9 FAULT DIAGNOSIS 227
9.1 Fault Location 228
9.2 Diagnostic Test Generation 238
9.3 Diagnostic Fault Simulation 240
9.4 Dynamic diagnosis 254
10 INSTRUMENTATION FOR I
DDQ
MEASUREMENT 263
(Contributed by: Kenneth M. Wallquist)
10.1 Introduction 264
10.2 The Instrumentation Puzzle 264
10.3 Things to Consider 266
10.4 Degrading Factors 267
10.5 IDDQ vs. ISSQ Measurement 269
10.6 Historical Methods ofMeasuring IDDQ 270
10.7 Advanced Tester-Based Instrumentation 278
10.8 Loadboard-Mounted Instrumentation 280
10.9 Conclusion 286
REFERENCES 287
INDEX 317
FOREWORD
The completeness of this book signals a maturity for that innovation in elec
tronic testing of CMOS integrated circuits (ICs) called IDDQ testing. Today
we recognize the IDDQ test as the single most sensitive method for detecting
defects in CMOS ICs. IDDQ testing has a simple concept; the quiescent or
steady state portion of a CMOS circuit clock period should have a very low
power current since there are no continuous circuit paths between the VDD
power rail and the VSS ground. Quiescent currents ofgood circuits are at the
sub microAmp level and typically can be tens ofnanoAmps. Ifhigh J.1-A or rnA
currents exist at a particular vector state, then the circuit isn't correct. Frank
Wanlass, who patented the CMOS technology in 1963, described CMOS cir
cuits asa nanoWattlogic. Onecouldextrapolatefrom Wanlass that ifa CMOS
circuit didn't measure low quiescent currents, then it must have a defect, or a
design or fabrication error.
Early in the history of CMOS Ie development in the 1960's, RCA practiced
IDDQ testing on its CD4000 line ofSSI/MSI parts. Philips Labs, Rome Labs,
and SandiaNational Labsactively used this technique inthe 1970s,despite the
fact that an electronic basis for the IDDQ test practice had yet to be demon
strated. Except for George Nelson, E. King, and William Boggs of the US
Naval Research Labs, publications in the 1970's were rare and little exchange
among people occurred. That changed around 1980 when CMOS began to re
placenMOSas thedominant IC technology. TheInternationalTest Conference
(ITC) attracted an initially small, but growing number oftest engineers inter
estedinthe topic. MarkLeviin 1981,andYashwantMalaiyaandStephenSuin
1982,presentedaggressivepapersatITCoutliningthebenefitsofIDDQ testing.
Around 1981, Toshio Maruyama of Advantest Corp. designed the first IDDQ
monitor for ATE that was fast and sensitive. His IDDQ Bit Current Option
could read a 1J.1-A sensitivity at a 3-5 kHz measurement rate. Activity picked
up in the mid-1980's. John Zasio's (then at AIDA Corp.) succinct COMPCON
paper in 1985 was a precursor to modern thinking about defect-based testing,
IDDQ, and stuck-at faults. In a series of papers from 1985-91, Jerry Soden of
SandiaNationalLabs and ChuckHawkinsofthe UniversityofNew Mexicoand
xi
XlI INTRODUCTION TO IDDQ TESTING
colleagues at Sandia presented data showing the effectiveness of IDDQ testing
for specific CMOS defects. Mircille Jacomino, Jean Luc Rainard, and Rene
David of the Lab d'Automatique de Grenoble and Centre Nat. d'Etudes des
Telecom. also made comprehensive conclusions on varieties of test methods
including IDDQ'
In the 1990 era, major contributions to understanding the IDDQ technique
have come from Peter Maxwell, Rob Aitken, and Doug Josephson ofHewlett
Packard, Keith Baker, Manoj Sachdev, Eric Bruls, and Bas Verhelst ofPhilips
Labs, Wociech Maly and Anne Gattiker of Carnegie Mellon University, Alan
Righter, Chris Henderson, Ron Fritzemeier, and Dick Beagle of Sandia Na
tional Labs, Phil Nigh ofIBM, Steve McEuen, Ravi Gulati, and Weiwei Mao
of Ford Microelectronics, Sreejit Chakravarty of the State University of New
Yorkat Buffalo, KenWallquistandGraysonGarrettofPhilipsSemiconductors,
Keiichi Sawada of Mitsubishi, Roger Perry of Storagetek, Ric Gayle of NCR,
Joan Figueras, Antonio Rubio, Jaume Segura, Rosa Rodriguez-Montanes, Vic
tor Champac, and Eugene Isern from the Universitat Politecnicade Catelonia,
Paul Wiscombe of VLSI Technology, Carol Tong of Sunrise, Ben Bennetts of
LogicVision, Michael Keating of GenRad, Dan Burns of Rome Lab, Ed Mc
Cluskey and Hong Hao of Stanford University, Tom Storey of Loral Federal
Systems, Vic Kulkarni of Crosscheck, Rochit Rajsuman of LSI Logic, Simon
Johnson of the University of Durham, Hans Manhaeve at the University of
Oostende, Jacob Abraham ofthe University ofTexas, Wayne Needham, Tony
Miller, Wendy Whitman, John Acken, Tim Henry, and Thomas Soo of Intel,
Joel Ferguson and Tracey Larabee ofthe University of California-Santa Cruz,
Anura Jayasumana of Colorado State University, H. Vierhaus ofthe German
National Research Centerfor CS, Sankaran Menon oftheSouth DakotaSchool
ofMines &Technology, Jos van Sas and colleaguesfrom Alcatel, Adit Singh of
Auburn University, Kozo Kinoshita of Osaka University, Andrew Richardson
of Lancaster University, Bob Gruebel, Ken Butler and Theo Powell of Texas
Instruments, M. Renovell and G. Cambon of the Universite des Sciences et
TechniquesduLanguedoc,ScottDavidsonatAT&T,Jim FrenzeloftheUniver
sity ofIdaho, JeffBeasley ofNew Mexico State University, Shobha Mallarapu,
Albert Hoffman, S. Duey, and colleagues from Delco Electronics, and Rinya
Kawahara, Osamu Nakayama, and Tatsuru Kurasawafrom Kawasaki Steel.
These collective studies from around the world showed the following. IDDQ is
presently the only practical and guaranteed method ofdetecting the dominant
defect in IC manufacturing, namely the bridging defect, and certain forms
of CMOS open circuit defects are only detected by IDDQ testing. Several