Introduction to Digital Electronics (Essential Electronics Series)

333 Pages·1998·12.49 MB·English

by  John Crowe

Introduction to Digital Electronics
Introduction to Digital Electronics
This Page Intentionally Left Blank
Introduction to Digital
Electronics
John Crowe and Barrie Hayes-Gill
Both Lecturers in the
Department of Electrical and Electronic Engineering
University of Nottingham
Nownes
OXFORD AMSTERDAM BOSTON LONDON NEW YORK PARIS
SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO
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Contents
Series preface xi
Preface xii
Acknowledgements xii
Chapter I Fundamentals 1
1.1 Introduction 1
1.2 Basic principles 1
1.2.1 Boolean algebra- an introduction 1
1.2.2 The three Boolean operators 2
1.3 Boolean algebra 4
1.3.1 Single-variable theorems 4
1.3.2 Multivariable theorems 7
1.4 Logic symbols and truth tables 12
1.5 Timing diagrams 16
1.6 Duality and gate equivalence 18
1.7 Positive and negative assertion level logic 23
1.8 Universal gates 25
1.9 Self-assessment 26
1.10 Problems 27
Chapter 2 Arithmetic and digital electronics 29
2.1 Introduction 29
2.2 Bases-2, 10 and 16 (binary, decimal and hexadecimal) 29
2.2.1 Conversion from base-n to decimal 29
2.2.2 Conversion from decimal to base-n 31
2.2.3 Binary and hexadecimal 32
2.3 Other binary coding systems 33
2.4 Output from analogue-to-digital converters 35
2.5 Binary arithmetic 36
2.5.1 Addition 36
2.5.2 Subtraction 37
2.5.3 Multiplication 42
2.5.4 Division 43
2.6 Self-assessment 43
vi Contents
2.7 Problems 44
Chapter 3 Combinational logic basics 46
3.1 Introduction 46
3.2 Combinational logic theory 48
3.2.1 Fundamental sum of products expressions 48
3.2.2 Two-level circuits 49
3.2.3 Minimisation of fundamental sum of products expressions 50
3.2.4 Summary 52
3.3 Minimisation of combinational logic expressions 52
3.3.1 Minimisation via Boolean algebra 53
3.3.2 Minimisation via Karnaugh maps 54
3.3.3 Minimisation via the Quine-McCluskey technique 72
3.4 Product of sums: the negative logic approach 77
3.5 Self-assessment 84
3.6 Problems 85
Chapter 4 Combinational logic circuits 88
4.1 Common combinational logic circuits 88
4.1.1 Multiplexers 88
4.1.2 Demultiplexers 92
4.1.3 Encoders 94
4.1.4 XOR gate based circuits 96
4.1.5 Full adders 98
4.2 Combinational logic design example: a four-bit adder 100
4.2.1 Two-level circuits 100
4.2.2 Specification for the four-bit binary adder 101
4.2.3 Two-level circuit implementation 101
4.2.4 Heuristic implementation 102
4.2.5 Summary 107
4.3 Hazards 108
4.3.1 Introduction 108
4.3.2 Static hazards 109
4.3.3 Dynamic hazards 116
4.3.4 Summary 119
4.4 Self-assessment 120
4.5 Problems 120
Chapter 5 Asynchronous sequential logic 125
5.1 Sequential logic circuits: an overview 125
5.1.1 Asynchronous and synchronous circuits 126
5.2 Introduction to asynchronous sequential circuits 128
5.2.1 Inputs and race conditions 129
5.3 Analysis 129
Contents vii
5.3.1 Circuit 1: stable and unstable states 129
5.3.2 Circuit 2: movement between states 130
5.3.3 Circuit 3: memory 131
5.3.4 Circuit 4: rigorous analysis 133
5.3.5 Summary of analysis procedure 138
5.3.6 Circuit 5: two internal inputs 138
5.4 Circuit 6: a binary storage element 142
5.4.1 Analysis 142
5.4.2 Race conditions 144
5.4.3 The SR flip-flop 145
5.5 Introduction to asynchronous sequential circuit design 146
5.6 Self-assessment 148
5.7 Problems 148
Chapter 6 Flip-flops and flip-flop based circuits 150
6.1 Introduction 150
6.1.1 Flip-flop types 150
6.1.2 Flip-flop operation 151
6.1.3 Timing requirements 153
6.1.4 Other inputs 153
6.2 Single flip-flop applications 154
6.2.1 Switch debouncing 154
6.2.2 Pulse synchroniser 156
6.3 Registers 158
6.3.1 Shift registers 158
6.3.2 Application of shift registers 160
6.4 Self-assessment 161
6.5 Problems 162
Chapter 7 Counters 164
7.1 Introduction 164
7.1.1 Asynchronous and synchronous counters 164
7.2 Asynchronous counters 165
7.2.1 Mod-N asynchronous counters 166
7.3 Mod-2" synchronous counters 167
7.3.1 Implementation of the steering logic 168
7.4 Mod-N synchronous counters 169
7.4.1 Mod-8 counter using D-type flip-flops 169
7.4.2 Mod-8 counter using JK flip-flops 169
7.5 Example: mod-6 counter 173
7.5.1 D-type implementation 173
7.5.2 JK-type implementation 175
7.6 Self-assessment 177
7.7 Problems 177
viii Contents
Chapter 8 Synchronous sequential circuits 179
8.1 Introduction 179
8.2 Classification 180
8.2.1 Autonomous circuits 180
8.2.2 General (Moore and Mealy)circuits 180
8.3 Design examples 181
8.3.1 Autonomous circuit 181
8.3.2 Moore model circuit 183
8.4 Analysis 185
8.4.1 Case 1 185
8.4.2 Case 2 186
8.5 Summary 187
8.6 Self-assessment 188
8.7 Problems 188
Chapter 9 Choosing a means of implementation 191
9.1 Introduction 191
9.2 The bipolar junction transistor 193
9.2.1 The BJT as a switch 193
9.2.2 The BJT as a logic gate 194
9.3 The MOSFET 204
9.3.1 The MOSFET as a switch 204
9.3.2 The MOSFET as a logic gate 207
9.3.3 CMOS inverter 208
9.3.4 CMOS logicgates 211
9.3.5 Complex gates with CMOS 212
9.3.6 CMOS transmission gate 215
9.3.7 CMOS 4000 series logic 216
9.3.8 CMOS 74 serieslogic 217
9.4 BiCMOS- The best of both worlds 219
9.5 Low-voltage operation 220
9.6 Other technology options 221
9.6.1 Emitter coupled logic- ECL 221
9.6.2 Gallium arsenide- GaAs 222
9.7 Gate characteristics 223
9.7.1 Transfer characteristics 223
9.7.2 Noise margin 224
9.7.3 Output drive (fan out/fan in) 225
9.7.4 Propagation delay 226
9.7.5 Power dissipation 228
9.8 Open collector and three-state logic 229
9.8.1 Open collector/drain 230
9.8.2 Three-state logic 231
9.9 Comparisons of logic families 232
Contents ix
9.10 Miscellaneous practical problems 234
9.10.1 Interfacing 234
9.10.2 Unused inputs 236
9.10.3 Decoupling 237
9.11 Self-assessment 237
9.12 Problems 238
Chapter 10 Semiconductor memories 240
10.1 Introduction 240
10.2 Read only memory- ROM 242
10.2.1 Mask programmed ROMs 242
10.2.2 PROMs 246
10.2.3 EPROM 248
10.2.4 E2PROM 250
10.2.5 FLASH E:PROM 253
10.3 Random access memory- RAM 255
10.3.1 Static RAMs 256
10.3.2 Dynamic RAMs 258
10.4 Memory modules 263
10.5 Selecting the appropriate memory 263
10.6 Self-assessment 264
10.7 Problems 265
Chapter 11 Selecting a design route 266
11.1 Introduction 266
11.1.1 Brief overview of design routes 266
11.2 Discrete implementation 268
11.2.1 Spikes and glitches 269
11.2.2 Monostables 270
11.2.3 CR pulse generator 274
11.3 Mask programmable ASICs 275
11.3. ! Safe design for mask programmable ASICs 275
11.3.2 Mask programmable gate arrays 278
11.3.3 Standard cell 284
11.3.4 Fullcustom 286
11.4 Field programmable logic 287
11.4.1 AND-OR programmable architectures 287
11.4.2 ROM: fixed AND-programmable OR 288
11.4.3 PAL: programmable AND-fixed OR 291
11.4.4 PLA: programmable AND-programmable OR 293
11.4.5 Field programmable gate arrays 295
11.4.6 CAD tools for field programmable logic 299
11.5 VHDL 302
11.6 Choosing a design route 304