Intel® 64 Architecture x2APIC Specification

35 Pages·2010·0.254 MB·English

by  coll.

Intel® 64 Architecture x2APIC
Specification
Reference Number: 318148-004
March 2010
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INTRODUCTION
CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION
The xAPIC architecture provided a key mechanism for interrupt delivery in many
generations of Intel processors and platforms across different market segments. This
document describes the x2APIC architecture which is extended from the xAPIC archi-
tecture (the latter was first implemented on Intel® Pentium® 4 Processors, and
extended the APIC architecture implemented on Pentium and P6 processors). Exten-
sions to the xAPIC architecture are intended primarily to increase processor addres-
sability. The x2APIC architecture provides backward compatibility to the xAPIC
architecture and forward extendability for future Intel platform innovations. Specifi-
cally, x2APIC
•
Retains all key elements of compatibility to the xAPIC architecture:
— delivery modes,
— interrupt and processor priorities,
— interrupt sources,
— interrupt destination types;
•
Provides extensions to scale processor addressability for both the logical and
physical destination modes;
•
Adds new features to enhance performance of interrupt delivery;
•
Reduces complexity of logical destination mode interrupt delivery on link based
architectures.
1.2 IMPACTED PLATFORM COMPONENTS
x2APIC is architected to extend from the xAPIC architecture while minimizing the
impact on platform components. Specifically, support for the x2APIC architecture can
be implemented in the local APIC unit. All existing PCI/MSI capable devices and
IOxAPIC unit should work with the x2APIC extensions defined in this document. The
x2APIC architecture also provides flexibility to cope with the underlying fabrics that
connect the PCI devices, IOxAPICs and Local APIC units.
The extensions provided in this specification translate into modifications to:
•
the local APIC unit,
•
the underlying fabrics connecting Message Signaled Interrupts (MSI) capable PCI
devices to local xAPICs,
•
the underlying fabrics connecting the IOxAPICs to the local APIC units.
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INTRODUCTION
However no modifications are required to PCI or PCIe devices that support direct
interrupt delivery to the processors via Message Signaled Interrupts. Similarly no
modifications are required to the IOxAPIC. The routing of interrupts from these
devices in x2APIC mode leverages the interrupt remapping architecture specified in
the Intel Virtualization Technology for Directed I/O, Rev 1.1 specification.
Modifications to ACPI interfaces to support x2APIC are described in the ACPI 4.0
specification.
1.3 GLOSSARY
This document uses the terms listed in the following table.
Table 1-1. Description of terminology
Term Description
The set of advanced programmable interrupt controller features which
may be implemented in a stand-alone controller, part of a system chipset,
APIC or in a microprocessor.
The processor component that implements the APIC functionalities. The
underlying APIC registers their functionalities are documented in Chapter
8 of “Intel® 64 and IA-32 Architectures Software Developer’s Manual“, Vol.
3B. Historically, this may refer narrowly to early generations of processor
component in the Pentium and P6 processors. In this document, we also
use this term generically across multiple generations of processor
local APIC components.
The system chipset component that implements APIC functionalities to
I/O APIC communicate with a local APIC.
The extension of the APIC architecture that includes messaged APIC
interface over the system bus and expanding processor physical
xAPIC addressability from 4 bits to 8 bits.
The processor component that implements the associated xAPIC
functionalities. This is supported by Intel® Pentium® 4 processors,
Pentium® M processors, Intel® CoreTM 2 Duo processors, and Intel® Xeon®
processors based on Intel® NetBurst microarchitecture and Intel® CoreTM
local xAPIC microarchitecture.
The extension of xAPIC architecture to support 32 bit addressability of
x2APIC processors and associated enhancements.
The processor component that implements the associated x2APIC
local x2APIC functionalities.
The operating mode of a local xAPIC unit when it is enabled, or that of a
xAPIC mode local x2APIC unit when it is enabled but not in extended mode.
The operating mode of a local x2APIC unit when it is enabled and in
x2APIC mode extended mode.
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INTRODUCTION
Table 1-1. Description of terminology
Term Description
A unique ID that can identify individual agent in a platform (or clustered
configuration). The maximum bit-width supported is 8 bit, versus 32 bits
APIC ID in x2APIC.
The value configured in the local APIC ID register in xAPIC mode. This is an
8-bit value for xAPIC, and x2APIC in xAPIC mode. Because this is used to
specify a target destination in physical delivery mode, it is also referred to
local xAPIC ID as physical xAPIC ID. The processor initializes local xAPIC ID.
physical xAPIC ID See “local xAPIC ID”.
The APIC ID value that specifies a target processor to receive interrupt
delivered in logical destination mode in a local xAPIC. See documentation
on logical destination register (LDR) in Section 2.4.2. This is an 8-bit value.
logical xAPIC ID Logical xAPIC ID is not initialized by hardware.
The value reported by CPUID.01H:EBX[31:24]. Initial APIC ID is initialized
initial APIC ID by hardware.
The 32-bit value in the local APIC ID register defined by the x2APIC
architecture. The value is initialized by hardware and can be accessed via
RDMSR in x2APIC mode. It is also reported by CPUID.0BH:EDX. Application
x2APIC ID can query CPUID.0BH:EDX in user mode without RDMSR.
The APIC ID value that specifies a target processor to receive interrupt
delivered in logical destination mode in a local x2APIC. This is a 32-bit
logical x2APIC ID value initialized by hardware.
RsvdZ Reads of reserved bits return zero
1.4 REFERENCES
• Intel® 64 and IA-32 Architectures Software Developer’s Manual (in five volumes)
http://developer.intel.com/products/processor/manuals/index.htm
•
Intel Virtualization Technology for Directed I/O, Rev 1.1 specification
http://download.intel.com/technology/computing/vptech/Intel(r)_VT_for_Direc
t_IO.pdf
•
Detecting Multi-Core Processor Topology in an IA-32 Platform
http://www3.intel.com/cd/ids/developer/asmo-na/eng/recent/275339.htm
•
The ACPI 4.0 specification
http://www.acpi.info/spec.htm
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INTRODUCTION
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LOCAL X2APIC ARCHITECTURE
CHAPTER 2
LOCAL X2APIC ARCHITECTURE
2.1 X2APIC ENHANCEMENTS
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
•
Support for two modes of operation to provide backward compatibility and exten-
sibility for future platform innovations:
— In xAPIC compatibility mode, APIC registers are accessed through memory
mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
— In x2APIC mode, APIC registers are accessed through Model Specific Register
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly
increased processor addressability and some enhancements on interrupt
delivery.
•
Increased range of processor addressability in x2APIC mode:
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt
processor addressability up to 4G-1 processors in physical destination mode.
A processor implementation of x2APIC architecture can support fewer than
32-bits in a software transparent fashion.
— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical
x2APIC ID is partitioned into two sub-fields: a 16-bit cluster ID and a 16-bit
logical ID within the cluster. Consequently, ((2^20) -16) processors can be
addressed in logical destination mode. Processor implementations can
support fewer than 16 bits in the cluster ID sub-field and logical ID sub-field
in a software agnostic fashion.
•
More efficient MSR interface to access APIC registers.
— To enhance inter-processor and self directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR based interfaces in the x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in the x2APIC mode.
•
The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically
the software semantics for using the Interrupt Command Register (ICR) and End
Of Interrupt (EOI) registers have been modified to allow for more efficient
delivery and dispatching of interrupts.
The x2APIC extensions are made available to system software by enabling the local
x2APIC unit in the "x2APIC" mode. The rest of this chapter provides details for
detecting, enabling and programming features of x2APIC.
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LOCAL X2APIC ARCHITECTURE
2.2 DETECTING AND ENABLING X2APIC
A processor’s support to operate its local APIC in the x2APIC mode can be detected
by querying the extended feature flag information reported by CPUID. When CPUID
is executed with EAX = 1, the returned value in ECX[Bit 21] indicates processor’s
support for the x2APIC mode. If CPUID.(EAX=01H):ECX[Bit 21] is set, then the local
APIC in the processor supports the x2APIC capability and can be placed into the
x2APIC mode. This bit is set only when the x2APIC hardware is present.
•
System software can place the local APIC in the x2APIC mode by setting the
x2APIC mode enable bit (bit 10) in the IA32_APIC_BASE MSR at MSR address
01BH. The layout for the IA32_APIC_BASE MSR is shown in Figure 2-1.
63 3635 12111098 7 0
Reserved APIC Base
APIC Base—Base physical address
EN—xAPIC global enable/disable
EXTD—Enable x2APIC mode
BSP—Processor is BSP
Reserved
Figure 2-1. IA32_APIC_BASE MSR Supporting x2APIC
Table 2-1, “x2APIC operating mode configurations” describe the possible combina-
tions of the enable bit (EN - bit 11) and the extended mode bit (EXTD - bit 10) in the
IA32_APIC_BASE MSR.
Table 2-1. x2APIC Operating Mode Configurations
xAPIC global enable x2APIC enable
(IA32_APIC_BASE[11]) (IA32_APIC_BASE[10]) Description
0 0 local APIC is disabled
0 1 Invalid
1 0 local APIC is enabled in xAPIC mode
1 1 local APIC is enabled in x2APIC mode
Once the local APIC has been switched to x2APIC mode (EN = 1, EXTD = 1),
switching back to xAPIC mode would require system software to disable the local
APIC unit. Specifically, attempting to write a value to the IA32_APIC_BASE MSR that
has (EN= 1, EXTD = 0) when the local APIC is enabled and in x2APIC mode will raise
a GP exception. Once bit 10 in IA32_APIC_BASE MSR is set, the only way to leave
x2APIC mode using IA32_APIC_BASE would require a WRMSR to set both bit 11 and
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LOCAL X2APIC ARCHITECTURE
bit 10 to zero. Section 2.7, “x2APIC STATE TRANSITIONS” provides a detailed state
diagram for the state transitions allowed for the local APIC.
2.3 X2APIC MODE REGISTER INTERFACE
In xAPIC mode, the software model for accessing the APIC registers is through a
memory mapped interface. Specifically, the APIC registers are mapped to a 4K-Byte
region in the processor's memory address space, the physical address base of the
4K-Byte region is specified in the IA32_APIC_BASE MSR (Default value of
FEE0_0000H).
In x2APIC mode, a block of MSR address range is reserved for accessing APIC regis-
ters through the processor’s MSR address space. This section provides details of this
MSR based interface.
2.3.1 Instructions to Access APIC Registers
In x2APIC mode, system software uses RDMSR and WRMSR to access the APIC regis-
ters. The MSR addresses for accessing the x2APIC registers are architecturally
defined and specified in Section 2.3.2, “APIC Register Address Space”. Executing the
RDMSR instruction with APIC register address specified in ECX returns the content of
bits 0 through 31 of the APIC registers in EAX. Bits 32 through 63 are returned in
register EDX - these bits are reserved if the APIC register being read is a 32-bit
register. Similarly executing the WRMSR instruction with the APIC register address in
ECX, writes bits 0 to 31 of register EAX to bits 0 to 31 of the specified APIC register.
If the register is a 64-bit register then bits 0 to 31 of register EDX are written to bits
32 to 63 of the APIC register. The Interrupt Command Register is the only APIC
register that is implemented as a 64-bit MSR. The semantics of handling reserved
bits are defined in Section 2.3.3, “Reserved Bit Checking”.
2.3.2 APIC Register Address Space
The MSR address range between 0000_0800H through 0000_0BFFH is architectur-
ally reserved and dedicated for accessing APIC registers in x2APIC mode. Figure 2-2
provides the detailed list of the APIC registers in xAPIC mode and x2APIC mode. The
MSR address offset specified in the table is relative to the base MSR address of 800H.
The MMIO offset specified in the table is relative to the default base address of
FEE00000H.
There is a one-to-one mapping between the legacy xAPIC register MMIO offset and
the MSR address offset with the following exceptions:
•
The Interrupt Command Register (ICR): The two 32-bit ICR registers in xAPIC
mode are merged into a single 64-bit MSR in x2APIC mode.
•
The Destination Format Register (DFR) is not supported in x2APIC mode.
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LOCAL X2APIC ARCHITECTURE
•
The SELF IPI register is available only if x2APIC mode is enabled.
The MSR address space is compressed to allow for future growth. Every 32 bit
register on a 128- bit boundary in the legacy MMIO space is mapped to a single MSR
in the local x2APIC MSR address space. The upper 32-bits of all x2APIC MSRs (except
for the ICR) are reserved.
Table 2-2. Local APIC Register Address Map Supported by x2APIC
MSR Offset
MMIO Offset (x2APIC R/W
(xAPIC mode) mode) Register Name Semantics Comments
0000H- 000H-001H Reserved
0010H
0020H 002H Local APIC ID Register Read only See Section 2.7.1 for
initial values.
0030H 003H Local APIC Version Read only. Same version between
Register extended and legacy
modes. Bit 24 is available
only to an x2APIC unit (in
xAPIC mode and x2APIC
modes, See Section 2.5.1).
0040H- 004H-007H Reserved
0070H
0080H 008H Task Priority Register Read/Write. Bits 7:0 are RW. Bits 31:8
(TPR) are Reserved.
0090H 009H Reserved
00A0H 00AH Processor Priority Read only.
Register (PPR)
00B0H 00BH EOI Register Write only. 0 is the only valid value
to write. GP fault on non-
zero write
00C0H 00CH Reserved
00D0H 00DH Logical Destination Read only. Read/Write in xAPIC
Register mode)
00E0H 00EH Reserved1 GP fault on Read Write in
x2APIC mode.
00F0H 00FH Spurious Interrupt Read/Write. Bits 0-8, 12 Read/Write;
Vector Register other bits reserved.
0100H 010H In-Service Register Read Only.
(ISR); bits 0:31
0110H 011H ISR bits 32:63 Read Only.
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