Integrated Analog-To-Digital and Digital-To-Analog Converters

534 Pages·1994·34.47 MB·English

by  Rudy Van De Plassche (auth.)

INTEGRATED ANALOG-TO-DIGITAL
AND DIGITAL-TO-ANALOG CONVERTERS
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSIN G
Consulting Editor
Mohammed Ismail
Ohio State University
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INTEGRATED
ANALOG-TO-DIGITAL
AND
DIGITAL-TO-ANALOG
CONVERTERS
by
RUDY VAN DE PLASSCHE
Philips Research Laboratories, Eindhoven, The Netherlands
SPRINGER-SCIENCE+BUSINESS MEDIA, B.V.
A CLP. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4613-6186-2 ISBN 978-1-4615-2748-0 (eBook)
DOI 10.1007/978-1-4615-2748-0
Printed on acid-free paper
All Rights Reserved
© 1994 Springer Science+Business Media Dordrecht
Originally published by Kluwer Academic Publishers in 1994
No part of the material protected by this copyright notice may be reproduced or
utilized in any form or by any means, electronic or mechanical,
including photocopying, recording or by any information storage and
retrieval system, without written permission from the copyright owner.
Contents
List of figures xv
List of tables xxvii
List of symbols xxix
Preface xxxvii
1 The converter as a black box 1
1.1 Introduction ............... . 1
I AID
1.2 Basic D A and converter function . 2
1.3 Classification of signals 4
1.3.1 Analog signals ...... . 4
1.3.2 Discrete-time signals .. . 5
1.3.3 Amplitude-discrete signals 5
1.3.4 Digital signals ...... . 5
1.4 Sampling time uncertainty . 6
1.5 Sampling clock time uncertainty . 8
1.6 Quantization errors . . . . . . 10
1. 7 Oversampling of converters . . 14
1.8 Quantizer model. . . . . . . . 16
1.8.1 Quantizer phase uncertainty 17
1.8.2 Quantizer describing function model 19
1.9 Filtering................. 23
AID
1.9.1 Anti-alias filtering in converter systems. 25
1.9.2 Output filtering in D I A converter systems 27
1.10 Minimum required stop band attenuation. 33
1.11 Conclusion.......... . ..... 35
v
vi CONTENTS
2 Specifications of converters 37
2.1 Introduction ..... . 37
2.2 Digital data coding . . 38
2.3 Digital coding schemes 39
2.4 DC specifications . . . 41
2.4.1 Absolute accuracy ... 41
2.4.2 Relative accuracy . . . . 42
2.4.3 Nonlinearity calculation 43
2.4.4 Differential nonlinearity 48
2.4~ Ofucl........... 48
2.4.6 Temperature dependence . 49
2.4.7 Supply voltage .... 50
2.5 Dynamic specifications . . . 51
2.5.1 Signal-to-Noise Ratio ... 51
2.5.2 Spurious Free Dynamic Range . . 51
2.5.3 Dynamic range versus converter linearity . 54
2.5.4 Glitches ............ . 55
2.5.5 Noise ............. . 58
2.5.6 Minimum reference step size . 64
2.5.7 Bit Error Rate (BER) ... 65
2.5.8 Maximum sampling rate . . 66
2.5.9 Digital signal feed-through. 66
2.5.10 Distortion . . . . . . . . . . 67
2.5.11 Power supply rejection ratio 68
2.5.12 Settling time .. 69
2.5.13 Acquisition time .. . 69
2.5.14 Aperture time .... . 69
2.5.15 Sample-to-hold step .. 71
2.5.16 Droop rate ...... . 71
2.5.17 Signal feed-through during hold mode 72
2.5.18 Noise in sample-and-hold amplifiers .. 73
2.5.19 Overview of sample-and-hold specifications. 73
2.5.20 Analog system bandwidth ...... . 74
2.5.21 Differential gain and differential phase 76
2.6 Conclusion . . . . . . . . . . . . . . . . 76
I AID
3 Testing of D A and converters 79
3.1 Introduction ......... . 79
3.2 DC testing of D / A converters . . . . . 79
CONTENTS vii
3.2.1 Temperature relations ... 81
3.2.2 Supply voltage dependence. 81
3.2.3 Bit weight noise . . . . . . . 81
3.3 Dynamic testing of D I A converters 82
3.3.1 Dynamic integral nonlinearity test 83
3.3.2 Spurious free dynamic range . 83
3.3.3 Differential nonlinearity 84
3.3.4 Glitches .......... . 84
3.3.5 Distortion measurement . . 85
3.3.6 Settling time measurement. 85
3.4 DC testing of AID converters 87
3.5 Dynamic testing of AID converters 88
3.5.1 Conversion speed . . . . . . . . . 90
3.6 Bit Error Rate. . . . . . . . . . . . 91
3.7 Testing very high-speed AID converters 92
3.8 Beat frequency test configuration . . . . 95
3.9 Code density DNL and INL measurement 96
3.10 Testing of sample-and-hold amplifiers 100
3.10.1 Testing DC characteristics ..... . 100
3.10.2 Dynamic measurements ...... . 101
3.11 Cascading sample-and-hold amplifiers. 104
3.12 Conclusion ............... . 105
4 High-speed AID converters 107
4.1 Introduction ......... . 107
4.2 Design problems in high-speed converters. 110
4.2.1 Timing errors . . . . . . . . . . 110
4.2.2 Distortion . . . . . . . . . . . . III
4.3 Internal converter coding schemes 112
4.3.1 Thermometer code 112
4.3.2 Gray encoder . . . 112
4.3.3 Circular code . . . 114
4.4 Full-flash converters. 115
4.4.1 Bipolar comparator . 116
4.4.2 Bipolar full-flash converters 117
4.4.3 Improved bipolar comparator 121
4.4.4 MOS full-flash converters .. 121
4.4.5 Interleaved comparator full flash converter 125
4.4.6 Differential auto-zero comparator . . . . . 126
viii CONTENTS
4.5 Gray code full flash converters . 128
4.6 Circular code flash converters . 131
4.7 Two-step flash converters . . . . 132
4.7.1 Bipolar two-step AID converters 134
4.7.2 MOS two-step AID converters. . 135
4.7.3 Two-step AID with sample-and-hold comparator 137
4.7.4 Interleaved comparator two-step AID converter. . 139
4.7.5 Two-step recycling AID converter. . . . . . . . . . 142
4.7.6 BiCMOS two-step AID converter implementation. 144
4.8 Multi-step AID converter ......... 145
4.8.1 Bipolar five-step AID converter system. 146
4.9 Folding AID converters. . . . . . . . . . 148
4.9.1 Current-folding AID converter system 149
4.9.2 Parallel connection of quantizers 151
4.9.3 Fine quantizer circuit . . . 153
4.9.4 Fine encoder-latch circuit 154
4.9.5 Complete AID converter . 155
4.10 Double folding system ... 155
4.10.1 Practical double folding circuit . 156
4.10.2 Fine quantizer stages . . . . . . . . . 158
4.10.3 Delay-error correction ........ 159
4.10.4 Complete double folding AID converter . 160
4.11 Folding and interpolation systems. . . . 160
4.11.1 Voltage-folding AID converter system .. 163
4.11.2 Most Significant Bit generation . . . . . . 163
4.11.3 Practical folding and interpolation system 170
4.11.4 Optimal folding circuit implementation. . 172
4.11.5 Folding encoder circuit . . . 175
4.11.6 Interpolation circuit .... 177
4.11.7 Comparator architectures . 178
4.11.8 Circular-to-binaryencoder. 179
4.11.9 Bit synchronization between MSB, MSB-1, and LSB's 180
4.11.10 AID converter implementation . 182
4.11.11 Measurements. 183
4.11.12 Conclusion. . . . . . . . . 185
5 Limitations of comparators 189
5.1 Signal delay in limiting amplifiers 189
5.1.1 Introduction........... . 189
CONTENTS ix
5.2 Definition of the delay problem 190
5.3 Delay calculation model .. . 191
5.4 Variable delay calculation .. . 193
5.5 Distortion calculation . . . . . . 199
5.6 Failure analysis of comparators 204
5.6.1 First-order model of a flip-flop . 204
5.7 Input frequency decision moment variation . 208
5.8 Conclusion . . . . . . . . . . . . . . . . . . . 208
6 High-accuracy D / A converters 211
6.1 Introduction ........... . 211
6.2 Pulse-width modulation D / A converters 212
6.3 Integrating D / A converters. . . . . . . . 214
6.4 Current weighting using ladder networks 217
6.4.1 R-2R ladder network ......... . 218
6.4.2 Resistor weighting current network .. 219
6.4.3 Equal currents output ladder network 219
6.4.4 Data interleaved D / A converter . . . . . 221
6.4.5 Two-step current division network ... 222
6.4.6 Base dropping R-2R network with equal sized transistors. 223
6.4.7 10-bit binary-weighted converter system ...... . 224
6.4.8 Binary-weighted current divider using device scaling 226
6.4.9 MOS ladder network converter system ...... . 227
6.4.10 Weighted capacitor converter system . . . . . . . . 229
6.4.11 Some remarks about the ladder converter systems. 230
6.5 Monotonic by design network systems. 231
6.5.1 Current weighting operation . . . . 231
6.5.2 Voltage division operation . . . . . . 232
6.5.3 Dual-ladder 10-bit D/A converter .. 235
6.6 Self calibrating D / A converter system. 238
6.7 Dynamic Element Matching . . . . 240
6.7.1 Basic dynamic divider scheme . . . . 240
6.7.2 Practical dynamic divider circuit .. 243
6.7.3 Two-bit dynamic current divider scheme 244
6.7.4 High-speed Darlington switching stages. 247
6.7.5 Dynamic current mirror circuit ..... 248
6.7.6 Binary-weighted accurate current network 250
6.7.7 Binary-weighted current network with divided interchanging
clock ............................... . 251
x CONTENTS
6.7.8 Binary-weighted current network using equal interchanging
clock frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.7.9 14- and 16-bit binary network examples 253
6.7.10 Filtering and switching . . . . . . . . 255
6.7.11 Compensated bit switch . . . . . . . 256
6.7.12 Output current-to-voltage converter. 258
6.7.13 14-bit DIA parallel converter ... 258
6.7.14 16-bit dual DIA converter system .. 260
6.7.15 16-bit converter data ....... . 260
6.8 Current calibration principle . . . . . 262
6.8.1 Improved current calibration principle 265
6.8.2 Continuous current calibration system . . 265
6.8.3 Practical current calibration implementation . 266
6.8.4 16-bit DIA converter system ..... 267
6.8.5 Integral nonlinearity measurement . 268
6.8.6 Dynamic performance measurement. 268
I
6.8.7 D A converter specifications . 270
6.9 Conclusion . . . . . . . . . . . . . 270
7 High-accuracy AID converters 273
7.1 Introduction ............ . 273
7.2 Single slope AID converter system 274
7.3 Dual-slope AID converter system . 276
7.4 Dual-ramp single-slope AID converter system 277
7.4.1 Accuracy analysis of the dual ramp AID converter 279
7.5 Successive approximation converter system . . . . . . 280
7.5.1 Practical successive approximation AID converter. 281
7.5.2 Comparator-subtracter circuit ... 283
7.5.3 Complete practical AID converter 284
7.5.4 Measurements . . . . . . . . . . . . 284
7.6 Algorithmic AID converter. . . . . . 286
7.7 Cyclic Redundant Signed Digit AID converter . 291
7.8 Self-calibrating capacitor AID converter 294
7.9 Conclusion . . . . . . . . . . . . . . . . . 296
8 Sample-and-hold amplifiers 297
8.1 Introduction........ .. 297
8.2 Basic sample-and-hold configuration 298
8.2.1 Signal bandwidth ......... . 298