Implementation of flash analog-to-digital converters in silicon-on-insulator CMOS technology

191 Pages·2007·1.48 MB·English

by  Erik Sall.

Linko¨ping Studies in Science and Technology
Dissertations, No. 1093
Implementation of Flash
Analog-to-Digital Converters in
Sili
on-on-Insulator CMOS
Te
hnology
Erik S¨all
Department of Electrical Engineering
Linko¨ping University, SE–581 83 Linko¨ping, Sweden
Linko¨ping 2007
Implementation of Flash Analog-to-Digital Converters in
Sili
on-on-Insulator CMOS Te
hnology
Copyright c 2007 Erik S¨all
(cid:13)
[email protected]
http://www.es.isy.liu.se
Division of Electronics Systems
Department of Electrical Engineering
Linko¨pings universitet
SE–581 83 Linko¨ping
Sweden
ISBN 978-91-85715-18-3 ISSN 0345-7524
Printed by LiU-Tryck, Linko¨ping 2007
Abstra
t
A 130 nm partially depleted silicon-on-insulator (SOI) complementary
metal oxide semiconductor (CMOS) technology is evaluated with respect
to analog circuit implementation. We perform the evaluation through im-
plementation of three flash analog-to-digital converters (ADCs). Our study
indicatethattofullyutilizethepotentialperformanceadvantagesoftheSOI
CMOS technology the partially depleted SOI CMOS technology should be
replaced by a fully depleted technology. The manufacturing difficulties re-
garding the control of the thin-film thickness must however first be solved.
A strong motivator for using the SOI CMOS technology instead of bulk
CMOS seems to be the smaller gate leakage power consumption.
The targeted applications in mind for the ADCs are read channel and
ultra wideband radio applications. These applications requires a resolution
of at least four to six bits and a sampling frequency of above 1 GHz. Hence
the flash ADC topology is chosen for the implementations. In this work we
do also propose enhancements to the flash ADC converter. Further, this
work also investigates introduction of dynamic element matching (DEM)
into a flash ADC. A method to introduce DEM into the reference net of a
flash ADC is proposed and evaluated.
To optimize the performance of the whole system and derive the specifi-
cations for the sub-blocks of the system it is often desired to use a top-down
design methodology. To facilitate the top-down design methodology the
ADCs are modeled on behavioral level using MATLAB and SpectreHDL.
The modeling results are used to verify the functionality of the proposed
circuit topologies and serve as a base to the circuit design phase.
The first flash ADC implementation has a conventional topology. It has
a resistor net connected to a number of latched comparators and employs
a ones-counter thermometer-to-binary decoder. This ADC serves as a ref-
erence for evaluating the other topologies. The measurements indicate a
maximum sampling frequency of 470 MHz, an SNDR of 26.3 dB, and an
SFDR of about 29 to 35 dB.
The second ADC has a similar topology as the reference ADC, but its
thermometer-to-binarydecoderisbasedon2-to-1multiplexersbufferedwith
inverters. Thisgivesacompactdecoderwitharegularstructureandashort
critical path. The measurements show that it is more efficient in terms of
power consumption than the ones-counter decoder and it has 40 % smaller
chip area. Further, the SNDR and SFDR are similar as for the reference
ADC, but its maximum sampling frequency is about 660 MHz.
The third ADC demonstrates the introduction of DEM into the refer-
ence net of a flash ADC. Our proposed technique requires fewer switches
i
ii Abstra
t
in the reference net than other proposals. Our technique should thereby
be able to operate at higher sampling and input frequencies than compared
with the other proposals. This design yields information about the per-
formance improvements the DEM gives, and what the trade-offs are when
introducing DEM. Behavioral level simulations indicate that the SFDR is
improved by 11 dB in average when introducing DEM. The transistor level
simulations in Cadence and measurements of the ADC with DEM indicates
that the SFDR improves by 6 dB and 1.5 dB, respectively, when applying
DEM. The smaller improvement indicated by the measurements is believed
to be due to a design flaw discovered during the measurements. A mask
layer for the resistors of the reference net is missing, which affects their
accuracy and degrades the ADC performance. The same reference net is
used in the other ADCs, and therefore degrades their performance as well.
Hence the measured performance is significantly lower than indicated by
the transistor level simulations. Further, it is observed that the improved
SFDR is traded for an increased chip area and a reduction of the maximum
sampling frequency. The DEM circuitry impose a 30 % larger chip area.
A
knowledgments
First I thank my supervisor Professor Mark Vesterbacka for giving me the
opportunity to do this work and for his guidance and support during the
work. I also thank him for the valuable help in proofreading this thesis.
I also thank my past and present colleagues at the Division of Elec-
tronics Systems for their support, friendship, and for providing an inspiring
environment. For the same reasons I thank the rest of my colleagues I have
had cooperation with at the Department of Electrical Engineering.
I also thank Per-Erik F¨agerman at Mandalon Technologies AB, who
bonded the chips, for the the chip photos of the ADCs.
I thank all my friends for helping me to recharge my batteries when I
am not at work. I will hopefully see some of you in a strong thermal to the
sound of a happy variometer, climbing for the final glide after a day in the
sky.
A special thank to my parents Lennart and Birgitta, and my sisters
Ann-Sofie and Josefine for their support through the years. Even though
you might think you know what I have been doing for the past 4.5 years,
maybe this thesis can give you some more insight.
This work was supported by the MEDEA+ program, which financed
the chip manufacturing, and financially supported by STRINGENT and
the Swedish Research Council.
Erik Sa¨ll
Linko¨ping, March 22, 2007
iii

Abbreviations and Notation
This section lists the abbreviations and notation used in this thesis.
Abbreviations
ADC Analog-to-digital converter
BiCMOS Bipolar complementary metal oxide semiconductor
BOX Buried oxide
BSIM3SOI Berkeley short-channel IGFET model for SOI
CD Compact disc
CLK Clock
CMOS Complementary metal oxide semiconductor
DAC Digital-to-analog converter
DC Direct current
DEM Dynamic element matching
DUT Device under test
DVD Digital versatile disc
ENOB Effective number of bits
ERBW Effective resolution bandwidth
ESD Electrostatic discharge
FA Full adder
FD Fully depleted
FoM Figure of merit
GaAs Gallium arsenide
GSM Global system for mobile communications
HDD Hard disk drive
IGFET Insulated-gate field effect transistor
LNA Low noise amplifier
LPF Low-pass filter
LSB Least significant bit
MiM Metal insulator metal
MOSFET Metal oxide semiconductor field effect transistor
MSB Most significant bit
MUX Multiplexer
v
vi Abbreviations and Notation
NMOS Negative-channel metal oxide semiconductor
PCB Printed circuit board
PD Partially depleted
PLL Phase locked loop
PMOS Positive-channel metal oxide semiconductor
PRBS Pseudo-random bit stream
Q Quality factor
RF Radio frequency
ROM Read-only memory
SFDR Spurious-free dynamic range
SH Sample-and-hold
Si Silicon
SiO Silicon dioxide
2
SNDR Signal-to-noise and distortion ratio
SNR Signal-to-noise ratio
SOI Silicon-on-insulator
SOS Silicon-on-sapphire
SQNR Signal-to-quantization noise ratio
SSN Simultaneous switching noise
TH Track-and-hold
VGA Variable gain amplifier
Notation
A DC gain
0
C Parasitic capacitance between channel and body
ch,b
C Parasitic capacitance between the comparator inputs
comp,in
C Parasitic bottom junction area capacitance at the drain
db
C Parasitic capacitance between gate and channel
g,ch
C Parasitic capacitance between gate and source
gs
C Parasitic drain junction capacitance
j,d
C Parasitic source junction capacitance
j,s
C Parasitic sidewall junction capacitance
j,sw
Abbreviations and Notation vii
C Load capacitance
L
C Gate oxide capacitance per unit area
ox
C Parasitic bottom junction area capacitance at the source
sb
C Total C on the ADC input
tot comp,in
D Third order distortion
3
d Bit i in the digital output
i
D Digital output
out
dR Statistical deviation of the resistance
dV Statistical deviation of the reference net supply voltage
ref
f Preamplifier 3 dB bandwidth
amp
−
f Input frequency
in
f Maximum input frequency
in,max
f Sampling frequency
s
f Maximum sampling frequency
s,max
f Unity gain frequency
T
g Small signal drain-source conductance
ds
g Transistor transconductance
m
I Channel current
ch
I Total drain current
d
I DC drain current
D
I Drain saturation current
D,sat
I Reference bias current
ref
k Boltzmann’s constant
L Channel length
M Total number of output samples
M Rate of metastable states
n
n Body factor
N Total number of output bits, i.e., ADC resolution
N(0,σ) Gaussian distribution with zero mean and σ
standard deviation
p Reference net decoupling period, used in (5.6)
dec
P Distortion power
distortion
viii Abbreviations and Notation
P Noise power
noise
P Signal power
signal
P Power of the largest spurious
spurious,max
q The charge of an electron, i.e., the elementary charge
q Quantization error
e
q Feedthrough from input to reference net measured
LSB
in number of LSBs
q Quantization step
s
R Total reference net resistance
tot
R Unit resistance of a resistor in the reference net
u
∆t Timing difference between the clock and input signals
wires
T Temperature in Kelvin
t Propagation delay of a 2:1 MUX
MUX
t Sample time instants
n
t Oxide thickness
ox
∆t Sampling time uncertainty
s
t Critical path of the folded Wallace tree decoder
CP,folded
t Critical path of the MUX-based decoder
CP,MUX-decoder
t Critical path of the Wallace tree decoder
CP,Wallace
t Propagation delay of an XOR gate
XOR
V Early voltage
A
V Bias voltage
bias
V Supply voltage
DD
V Voltage between drain and source
ds
V ESD stress voltage
ESD
V Full-scale voltage
FS
V Voltage between gate and source
gs
V Input voltage
in
∆V Uncertainty in the sampled input voltage
in
V Linear range of the preamplifier
lr
V Voltage equivalent to one LSB
LSB