Hybrid Josephson CMOS FIFO by Amit Mehrotra Research Project

100 Pages·2010·1.39 MB·English

Hybrid Josephson CMOS FIFO
by
Amit Mehrotra
Research Project
Submitted to the Department of Electrical Engineering and Computer Sciences,
University of California at BERKELEY
in partial satisfaction of the requirements for the degree of Master of Sciences,
Plan II
Approval for the Report and Comprehensive Examination:
Committee:
Professor Theodore VanDuzer
Research Advisor
Date
* * * * * *
Professor Alberto L Sangiovanni-Vincentelli
Second Reader
Date
1
Hybrid Josephson CMOS FIFO
Amit Mehrotra
Abstract
We describe the design and measurement results of a hybrid Josephson-CMOS that adopts
a ring pointer architecture. The FIFO is designed for throughput at frequencies exceed-
ing 10 GHz in an optimized 4K 1.2 m m CMOS process. It consists of a CMOS memory
core surrounded by high-speed Josephson multiplexer-demultiplexer pair. We have used
split-output latch TSPC shift register as ring pointer for our FIFO. We have modified the
standard three-transistor CMOS DRAM cell to achieve a high-speed write and current-
mode read. We have developed a new Josephson-CMOS interface amplifier circuit which
achieves high throughput at reasonable power dissipations. We also have investigated the
design of the demultiplexer and the multiplexer.
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To my parents
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Contents
List of Figures vi
List of Tables viii
1 Introduction 1
1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Project Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Report Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 System Architecture 5
2.1 Functional Description of a FIFO . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 FIFO Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Event-Controlled Architecture . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Ring-Pointer Architecture . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Josephson-CMOS FIFO Architecture . . . . . . . . . . . . . . . . . . . . . . 9
2.4 System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Cold CMOS Device Properties 15
3.1 Process Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Carrier Statistics at Cryogenic Temperatures . . . . . . . . . . . . . . . . . 15
3.3 Threshold Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Subthreshold Conduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 Hot Carrier Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Ring Pointer Shift Register 23
4.1 True Single Phase Clock (TSPC) Edge Triggered Flip-Flops . . . . . . . . . 23
4.1.1 Double C2MOS Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.2 Split-Output Latch Flip-Flop . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Shift Register Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Design Specifications and Implementation . . . . . . . . . . . . . . . . . . . 27
4.3.1 Flip-Flop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.2 Clock Distribution Network Design . . . . . . . . . . . . . . . . . . . 28
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4.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Memory Cell 35
5.1 CMOS Memory Design at 4K . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1.1 Static Random Access Memory (SRAM) . . . . . . . . . . . . . . . . 35
5.1.2 Dynamic Random Access Memory (DRAM) . . . . . . . . . . . . . . 36
5.2 DRAM Modifications for Current Mode Read . . . . . . . . . . . . . . . . . 38
5.3 Design Specifications and Implementation . . . . . . . . . . . . . . . . . . . 38
5.4 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 Josephson-CMOS Interface Circuits 43
6.1 Interface Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2 Suzuki Stack Preamplification . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2.1 Suzuki Stack Structure. . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2.2 Suzuki Stack Biasing and Output Modification . . . . . . . . . . . . 46
6.3 Interface Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.4 Design Specification and Implementation. . . . . . . . . . . . . . . . . . . . 48
6.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.7 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.8 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7 Josephson Current Sense 61
7.1 Fundamentals of Zero Impedance Current Sensing . . . . . . . . . . . . . . 61
7.2 Single Ended Current Sensing Techniques . . . . . . . . . . . . . . . . . . . 62
7.3 4JL Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8 Josephson Demultiplexer 67
8.1 Edge Triggered Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.1.1 Clock Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
8.1.2 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.1.3 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.1.4 Buffered AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.2 Demultiplexer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.3 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9 Josephson Multiplexer 81
9.1 Multiplexer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.2 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10 Conclusions and Future Work 87
Bibliography 89
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List of Figures
2.1 Functional description of FIFO operation. . . . . . . . . . . . . . . . . . . . 6
2.2 Event controlled FIFO architecture. . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Ring pointer FIFO architecture.. . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Proposed Josephson-CMOS FIFO architecture. . . . . . . . . . . . . . . . . 10
2.5 Parallel FIFO block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 Write path timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Interconnect capacitance model.. . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Diffusion capacitance model. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Double C2MOS flip-flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Split-output latch flip-flop.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Circular shift register layout. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4 TSPC shift register cell with reset to “1” feature. . . . . . . . . . . . . . . . 26
4.5 TSPC shift register cell with reset to “0” feature. . . . . . . . . . . . . . . . 27
4.6 Two shift registers with skewed clocks. . . . . . . . . . . . . . . . . . . . . . 28
4.7 Output of the first and the second shift registers for different clock skews. . 29
4.8 Clock distribution network. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.9 Flip-Flop layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.10 Simulation of the complete read path. . . . . . . . . . . . . . . . . . . . . . 34
5.1 CMOS SRAM cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2 Three-transistor DRAM cell. . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3 One transistor DRAM cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.4 Three transistor DRAM cell with current mode read-out. . . . . . . . . . . 39
5.5 Three transistor DRAM cell layout. . . . . . . . . . . . . . . . . . . . . . . 40
5.6 Simulation results for the three transistor DRAM cell. . . . . . . . . . . . . 41
6.1 Interface architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.2 The Suzuki stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.3 Equivalent circuit of a resetting stack. . . . . . . . . . . . . . . . . . . . . . 46
6.4 CMOS bias for a Suzuki stack. . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.5 CMOS bias for a Suzuki stack with improved reset. . . . . . . . . . . . . . . 48
6.6 Stack output for standard and shunted CMOS loads. . . . . . . . . . . . . . 50
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6.7 Interface amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.8 Interface amplifier layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.9 Simulation results of interface amplifier. . . . . . . . . . . . . . . . . . . . . 53
6.10 Interface amplifier with calibration circuit. . . . . . . . . . . . . . . . . . . . 55
6.11 Timing diagram for interface calibration. . . . . . . . . . . . . . . . . . . . . 56
6.12 Simulation of interface calibration. . . . . . . . . . . . . . . . . . . . . . . . 57
6.13 Experimental results of the interface circuit operation at 10 MHz.. . . . . . 58
6.14 Experimental results of the interface circuit operation at 70 MHz.. . . . . . 59
7.1 Josephson junction I-V characteristics. . . . . . . . . . . . . . . . . . . . . . 61
7.2 Block diagram of single-ended current sensing. . . . . . . . . . . . . . . . . 63
7.3 MVTL based current sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.4 RCJL based current sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.5 4JL based current sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.6 Dynamic operation of a 4JL current sense element. . . . . . . . . . . . . . . 66
8.1 Clock shaping circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8.2 Regulation of a 10 GHz sinusoidal clock. . . . . . . . . . . . . . . . . . . . . 69
8.3 Edge-triggered buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
8.4 Simulation results for edge-triggered buffer. . . . . . . . . . . . . . . . . . . 71
8.5 Edge-triggered inverter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
8.6 Simulation results for edge-triggered inverter. . . . . . . . . . . . . . . . . . 74
8.7 Edge-triggered AND gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.8 Simulation results for edge-triggered AND gate. . . . . . . . . . . . . . . . . 76
8.9 Josephson demultiplexer architecture. . . . . . . . . . . . . . . . . . . . . . 77
8.10 Demultiplexer shift register simulation results.. . . . . . . . . . . . . . . . . 78
8.11 Shift register with read-out latches. . . . . . . . . . . . . . . . . . . . . . . . 79
8.12 Josephson demultiplexer simulation results. . . . . . . . . . . . . . . . . . . 80
9.1 Multiplexer architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.2 Circular shift register for the multiplexer. . . . . . . . . . . . . . . . . . . . 82
9.3 Circular shift register simulation results. . . . . . . . . . . . . . . . . . . . . 84
9.4 Simulation results for the complete demultiplexer. . . . . . . . . . . . . . . 85
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List of Tables
4.1 TSPC Shift Register Cell Device Parameters. . . . . . . . . . . . . . . . . . 32
4.2 Performance Measure of TSPC Shift Register. . . . . . . . . . . . . . . . . . 32
4.3 Clock Buffer Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 Interface Amplifier Device Parameters. . . . . . . . . . . . . . . . . . . . . . 49
6.2 Clock Buffer Sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 4JL current sense circuit parameters. . . . . . . . . . . . . . . . . . . . . . . 65
8.1 Edge-triggered buffer parameters. . . . . . . . . . . . . . . . . . . . . . . . . 70
8.2 Clock shaping circuit parameters for the edge-triggered buffer. . . . . . . . 70
8.3 Edge-triggered inverter parameters. . . . . . . . . . . . . . . . . . . . . . . . 73
8.4 Clock shaping circuit parameters for the edge-triggered inverter. . . . . . . 73
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Acknowledgements
I would like to thank my advisor Prof. Van Duzer for his constant support, guid-
ance and encouragement during the course of this research. I would also like to express my
sincere thanks to Prof. Sangiovanni-Vincentelli for his valuable feedback on this work.
I would like to thank Uttam Ghoshal and Kishore Seendripu for introducing me
to the topic of cold CMOS and for the interesting discussions we had during the course of
this project. I would like to thank Alex Flores for helping me in testing. I would also like
to thank other members of the hybrid group, Arnold Feldman and Hui Zhang for helping
me in various stages of this project.
My Berkeley experience has been a thoroughly rewarding one. I would like to
thank the people who were largely responsible for it - Alok Agrawal, Adnan Aziz, Anu
Bhat, Dubravka Bili´c, Mike Branch, Premal Buch, Luca Carloni, Edoardo Charbon, Yatin
Chawathe, John Deng, Jonathan Du, Alberto Ferrari, Keng Fong, Wilsin Gosti, Mark
Jeffrey, Sunil Khatri, Sriram Krishnan, Gurmeet Manku, Amit Marathe, Paolo Miliozzi,
Rajeev Murgai, Amit Narayan, Ashwin Nayak, Ali Niknejad, Willem Perold, Pramote
Piriyapoksombut, Mukul Prasad, Shaz Qadeer, Sriram Rajamani, Rajeev Ranjan, Jagesh
Sanghavi, Kumud Sanwal, Vigyan Singhal, Dennis Sinitsky, Osamu Takahashi, Zuoqin
Wang, Steve Whiteley and Phillip Xie.