high-speed pipelined adc using a bucket brigade front-end

117 Pages·2013·1.95 MB·English

HIGH-SPEED PIPELINED ADC USING
A BUCKET BRIGADE FRONT-END

A DISSERTATION
SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING
AND THE COMMITTEE ON GRADUATE STUDIES
OF STANFORD UNIVERSITY
IN PARTIAL FULFILLMENT OF THE REQUIREMENTS
FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY

Noam Dolev Geldbard
August 2013
© 2013 by Noam Dolev Geldbard. All Rights Reserved.

Re-distributed by Stanford University under license with the author.

This dissertation is online at: http://purl.stanford.edu/wp775fw8173

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I certify that I have read this dissertation and that, in my opinion, it is fully adequate
in scope and quality as a dissertation for the degree of Doctor of Philosophy.
Boris Murmann, Primary Adviser
I certify that I have read this dissertation and that, in my opinion, it is fully adequate
in scope and quality as a dissertation for the degree of Doctor of Philosophy.
Mohammad Arbabian
I certify that I have read this dissertation and that, in my opinion, it is fully adequate
in scope and quality as a dissertation for the degree of Doctor of Philosophy.
Bruce Wooley
Approved for the Stanford University Committee on Graduate Studies.
Patricia J. Gumport, Vice Provost for Graduate Education
This signature page was generated electronically upon submission of this dissertation in
electronic format. An original signed hard copy of the signature page is on file in
University Archives.
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Abstract

Advanced wireless technologies, such as LTE and LTE advanced, require low-
power, high-speed, and high-resolution analog-to-digital converters (ADCs). At present,
only the pipelined ADC architecture is capable of meeting the stringent bandwidth,
linearity, and resolution requirements for this application. However, in current products,
the power efficiency of this architecture is limited by the use of operational amplifiers as
inter-stage gain elements.
This research investigates an approach where the critical operational amplifiers
are replaced by a pulsed-based bucket brigade amplifier, which achieves voltage gain by
redistributing charge form a large sampling capacitor to a small load capacitor. This
circuit performs the residue amplification with lower power, but is weakly nonlinear and
therefore requires digital linearization. Since the power overhead for digital arithmetic in
modern CMOS technologies is low, this approach has the potential to yield large overall
power savings.
To evaluate this concept, a prototype ADC was implemented in 65-nm CMOS.
The converter operates at 200 MS/s, consumes 11.5 mW from a 1-V supply, and occupies
0.26 mm2. It achieves an SNDR of 65 dB at low input frequencies and 57.6 dB near
Nyquist, which corresponds to an SNDR-based Schreier FOM of 164.5 dB and 157 dB,
respectively. These results validate the concept of the proposed pulse-based bucket
brigade amplification, and the achieved performance compares favorably with the state of
the art.

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Acknowledgments

Being a graduate student at Stanford was one of the best experiences I had, and I
could not have done it without the help of many people that I want to thank here. First, I
want to thank my advisor Prof. Boris Murmann. It has been an honor being his student.
Having him as a mentor was the highlight of my experience in Stanford and I could not
achieve this without his help and guidance. I also want to thank Prof. Bruce Wooley and
Prof. Amin Arbabian for serving on my thesis reading committee and oral examination
committee. I want to thank Prof. Mark Horowitz for serving on the oral examination
committee and Prof. Norbert J. Pelc for chairing the oral examination committee.
For funding, I want to thank Renesas and C2S2 Focus Center (FCRP). Specially,
I want to thank Miki Takahiro from Renesas for his guidance and help. I want also to
thank TSMC for the fabrication of the prototype and Berkeley Design Automation for the
use of the Analog Fast SPICE Platform (AFS).
I want to thank Ann Guerra, our team administrative assistant. Ann always took
care for all the administrative tasks and helped to solve any problem in the best way. In
addition, I want to thank Joe Little, the computer system administrator. Joe always gave
the best solution for any computer problem, any day, any time of the day.
For current and former students in the team: Dr. Siddharth Seth, Dr. Alireza
Dastgheib, Dr. Donghyun Kim, Dr. Pedram Lajevardi, Dr. Ray Nguyen, Dr. Yoonyoung
Chun, Dr. Drew Hall, Dr. Justin Kyungryun Kim, Dr. Wei Xiong, Dr. Clay Daigle, Dr.
Manar El-Chammas, Dr. Parastoo Nikaeen, Dr. Yangjin Oh, Dr. Echere Iroaga, Vaibhav
Tripathi, Bill Chen, Kevin Zheng, Ryan Boesch, Nikolaus Hammler, Ross Walker, Alex
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Guo, Man-Chia Chen, Douglas Adams, Jonathon Spaulding, Alex Omid-Zohoor, Nishit
Harshad Shah, Valerie Barry, Lita Yang, Mahmoud Saadat, and Ilina Mitra, It has been
great experience working with all of them and I want to thank them for all the help and
support. Especially, I want to thank Dr. Jason Hu for introducing me to the world of
highly efficient pipeline ADCs, and to Martin Kramer for helping me design part of the
supporting circuits for the testchip.
I want to thank my parents, for guiding me through life and always driving me to
achieve the best out of me. I want to thank my wife, Einat, for going with me in this
journey and making it all possible. Thanks You. Last, but not least, I want to thank my
kids, Leaya and Dan who always reminded me that there is more to life than studies and
always put a smile on my face.

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Table of Contents

Abstract .............................................................................................................................. iv
Acknowledgments............................................................................................................... v
Table of Contents .............................................................................................................. vii
List of Tables ..................................................................................................................... xi
List of Figures ................................................................................................................... xii
List of Abbreviations ....................................................................................................... xvi
1. Introduction ............................................................................................................ 1
1.1. Motivation ....................................................................................................... 1
1.2. Background ..................................................................................................... 1
1.3. Pipeline ADC Inefficiencies ............................................................................ 3
1.4. Power Reduction Strategies ............................................................................. 7
1.4.1 Architecture Level .................................................................................... 7
1.4.2 Using Digital Circuitry for Power Reduction ........................................... 7
1.4.3 Amplifier Level......................................................................................... 8
1.4.4 The Quest for a Virtual Ground ................................................................ 8
1.5. Inspiration ...................................................................................................... 10
1.6. Organization .................................................................................................. 12
2. Bucket Brigade Circuit Basics ............................................................................. 13
2.1. Basic Operation ............................................................................................. 13
2.2. Bucket Brigade Circuit with Amplifier in Boosting Configuration .............. 15
2.3. Pulse-Based Bucket Brigade Amplifier......................................................... 16
2.3.1 Pulse Wave Shape ................................................................................... 17
2.3.2 Pulse-Based Bucket Brigade vs. Boosted Amplifier Configuration ....... 18
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2.3.3 Pulse-Based Bucket Brigade Amplifier Linearity .................................. 19
2.4. Summary ....................................................................................................... 21
3. The Bucket Brigade Amplifier ............................................................................. 22
3.1. Large Signal Analyses ................................................................................... 22
3.1.1 Constant V ............................................................................................ 23
G
3.1.2 Gain Function ......................................................................................... 26
3.1.3 RC-shaped V ......................................................................................... 26
g
3.2. Voltage Input vs. Charge Input ..................................................................... 29
3.2.1 Charge Input Scheme Overview ............................................................. 31
3.2.2 Gain Expression for the Charge Input Scheme ....................................... 32
3.3. Bias Voltages Value ...................................................................................... 33
3.4. Thermal Noise ............................................................................................... 36
3.4.1 Thermal Noise due to Sampling on C ................................................... 37
S
3.4.2 Thermal Noise due to Pre-charge of the Load Capacitor C .................. 37
L
3.4.3 Thermal Noise from Charge Redistribution Phase ................................. 37
3.5. Summary ....................................................................................................... 39
4. ADC Stage Design ............................................................................................... 40
4.1. Differential Implementation .......................................................................... 40
4.2. DAC Implementation .................................................................................... 42
4.2.1 DAC Linearity ........................................................................................ 42
4.2.2 DAC Thermal Noise ............................................................................... 46
4.2.3 DAC Layout Considerations ................................................................... 47
4.3. Sub-ADC Design ........................................................................................... 49
4.3.1 Multi-bit Implementation ........................................................................ 49
4.3.2 Comparator Implementation .......................................................................... 50
4.4. Timing ........................................................................................................... 51
4.4.1 Wave Shapes ........................................................................................... 54
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4.5. Summary ....................................................................................................... 55
5. Circuit Implementation ........................................................................................ 56
5.1. Top Level ...................................................................................................... 56
5.1.1 ADC High Level Architecture ................................................................ 56
5.1.2 Capacitor Sizing ...................................................................................... 57
5.2. Stage One ...................................................................................................... 58
5.2.1 Switch and Transistor Sizing .................................................................. 60
5.2.2 Stage 1 Comparators ............................................................................... 61
5.2.3 Calibration .............................................................................................. 63
5.3. Stage Two ...................................................................................................... 64
5.4. Stages 3-5: Bucket Brigade Circuit with Differential Boosting Amplifier ... 65
5.5. Stage Six ........................................................................................................ 70
5.6. Stages 7-13 .................................................................................................... 72
5.7. Summary ....................................................................................................... 73
6. Measurement Results ........................................................................................... 74
6.1. Introduction ................................................................................................... 74
6.2. Test Setup ...................................................................................................... 77
6.3. Measured Results .......................................................................................... 78
6.3.1 Dynamic Linearity .................................................................................. 78
6.3.2 Static Linearity ........................................................................................ 82
6.3.3 Thermal Noise......................................................................................... 83
6.3.4 Jitter ........................................................................................................ 85
6.3.5 Power ...................................................................................................... 87
6.3.6 Calibration Power ................................................................................... 88
6.4. Performance Summary .................................................................................. 89
6.5. Performance Comparison .............................................................................. 90
6.6. Summary ....................................................................................................... 93
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7. Conclusion ........................................................................................................... 94
7.1. Summary ....................................................................................................... 94
7.2. Future Work .................................................................................................. 95
8. Bibliography ........................................................................................................ 97

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