High Speed Op-amp Design: Compensation and - CMOSedu.com

58 Pages·2007·1.38 MB·English

by  R. Jacob Baker

High Speed Op-amp Design: Compensation and
Topologies for Two and Three Stage Designs
R. Jacob Baker and Vishal Saxena
Department of Electrical and Computer Engineering
Boise State University
1910 University Dr., MEC 108
Boise, ID 83725
[email protected] and [email protected]
Abstract :
As CMOS technology continues to evolve, the supply voltages are decreasing while at
the same time the transistor threshold voltages are remaining relatively constant. Making
matters worse, the inherent gain available from the nano-CMOS transistors is dropping.
Traditional techniques for achieving high gain by vertically stacking (i.e. cascoding)
transistors becomes less useful in sub-100nm processes. Horizontal cascading (multi-
stage) must be used in order to realize op-amps in low supply voltage processes.
This seminar discusses new design techniques for the realization of multi-stage op-amps.
Both single- and fully-differential op-amps are presented where low power, small
VDD, and high speed are important. The proposed, and experimentally verified, op-
amps exhibit significant improvements in speed over the traditional op-amp designs
while at the same time having smaller layout area.
Baker/Saxena
Outline
(cid:137)Introduction
(cid:137)Two-stage Op-amp Compensation
(cid:137)Multi-stage Op-amp Design
(cid:137)Multi-stage Fully-Differential Op-amps
(cid:137)Conclusion
Baker/Saxena
Op-amps and CMOS Scaling
(cid:137) The Operational Amplifier (op-amp) is a fundamental building
block in Mixed Signal design.
(cid:57) Employed profusely in data converters, filters, sensors, drivers etc.
(cid:137) Continued scaling in CMOS technology has been challenging
the established paradigms for op-amp design.
(cid:137) With downscaling in channel length (L)
(cid:57) Transition frequency increases (more speed).
(cid:57) Open-loop gain reduces (lower gains).
(cid:57) Supply voltage is scaled down (lower headroom) [1].
Baker/Saxena
CMOS Scaling Trends
(cid:137) VDD is scaling down but V is almost constant.
THN
(cid:57) Design headroom is shrinking faster.
(cid:137) Transistor open-loop gain is dropping (~10’s in nano-CMOS)
(cid:57) Results in lower op-amp open-loop gain. But we need gain!
(cid:137) Random offsets due to device mismatches.
[3], [4].
Baker/Saxena
Integration of Analog into Nano-CMOS?
(cid:137) Design low-VDD op-amps.
(cid:57) Replace vertical stacking (cascoding) by horizontal cascading of gain
stages (see the next slide).
(cid:137) Explore more effective op-amp compensation techniques.
(cid:137) Offset tolerant designs.
(cid:137) Also minimize power and layout area to keep up with the
digital trend.
(cid:137) Better power supply noise rejection (PSRR).
Baker/Saxena
Cascoding vs Cascading in Op-amps
A Telescopic Two-stage Op-amp
A Cascade of low-VDD
Amplifier Blocks.
(Compensation not shown here)
VDD VDD VDD VDD VDD VDD
VDD
2 n-1
1
vm vp n vout
CL
Vbiasn Vbiasn Vbiasn
Stage 1 Stage 2 Stage (n-1) Stage n
VDD >4V +V +V with
min ovn ovp THP VDD =2V +V +V
min ovn ovp THP.
wide-swing biasing. [1]
(cid:137) Even if we employ wide-swing biasing for low-voltage designs, three- or
higher stage op-amps will be indispensable in realizing large open-loop DC
gain.
Baker/Saxena
TWO-STAGE OP-AMP COMPENSATION
Baker/Saxena
Direct (or Miller) Compensation
(cid:137) Compensation capacitor (C )
c
VDD VDD between the output of the gain stages
VDD
causes pole-splitting and achieves
M3 M4 M7
1 dominant pole compensation.
220/2
750Ω
v v i (cid:137) An RHP zero exists at
m p Cfb v
M1 M2 out
(cid:57) Due to feed-forward component of
C
C
i 10pF 2 L
C C the compensation current (i ).
ff 30pF
C
V
bias3 (cid:137) The second pole is located at
M6TL 100/2
M6TR M8T
V
M6BL bias4 100/2 (cid:137) The unity-gain frequency is
M6BR M8B
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2. x10
(cid:153)All the op-amps presented have been designed in AMI C5N 0.5μm CMOS process with scale=0.3 μm and L =2.
min
The op-amps drive a 30pF off-chip load offered by the test-setup.
Baker/Saxena
Drawbacks of Direct (Miller) Compensation
(cid:137) The RHP zero decreases phase
VDD VDD
margin
VDD
M3 M4 M7 (cid:57) Requires large C for
1
C
220/2
compensation (10pF here for a
30pF load!).
v v C
m p C v
M1 M2
out
C (cid:137) Slow-speed for a given load, C
10pF 2 L L.
30pF
(cid:137) Poor PSRR
V
bias3
M6TL 100/2
M6TR M8T (cid:57) Supply noise feeds to the output
V
M6BL bias4 100/2 through C .
M6BR M8B C
(cid:137) Large layout size.
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
x10
Baker/Saxena
Indirect Compensation
VDD VDD VDD (cid:137) The RHP zero can be eliminated by
VDD
blocking the feed-forward compensation
M3 M4 M9
1 M7 current component by using
220/2
(cid:57) A common gate stage,
v
m M1 M2 ic Cc
2 vout (cid:57) A voltage buffer,
M
CG
v A CL
p (cid:57) Common gate “embedded” in the
30pF
V
M6TL bias3 100/2 cascode diff-amp, or
M6TR M10T M8T
V
M6BL bias4 100/2 (cid:57) A current mirror buffer.
M6BR M10B M8B
(cid:137) Now, the compensation current is fed-
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2. x10 back from the output to node-1 indirectly
through a low-Z node-A.
An indirect-compensated op-amp
using a common-gate stage. (cid:137) Since node-1 is not loaded by C , this
C
results in higher unity-gain frequency
(f ).
un
Baker/Saxena