High Speed Op-Amp Design

59 Pages·2015·3.87 MB·English

by  Talarico, Claudio

High Speed Op-Amp Design: Compensation and
Topologies for Two and Three Stage Designs
Distinguished Lecture

R. Jacob (Jake) Baker (UNLV, [email protected])
Abstract :
As CMOS technology continues to evolve, the supply voltages are decreasing
while at the same time the transistor threshold voltages are remaining relatively
constant. Making matters worse, the inherent gain available from the nano-
CMOS transistors is dropping. Traditional techniques for achieving high gain
by vertically stacking (i.e. cascoding) transistors becomes less useful in
sub-100nm processes. Horizontal cascading (multi-stage) must be used in
order to realize op-amps in low supply voltage processes. This seminar
discusses new design techniques for the realization of multi-stage op-amps.
Both single- and fully-differential op-amps are presented where low
power, small VDD, and high speed are important. The proposed, and
experimentally verified, op-amps exhibit significant improvements in
speed over the traditional op-amp designs while at the same time having
smaller layout area.
IEEE Solid-State Circuits Society – Gonzaga, April 9-10, 2015 1
Outline Distinguished Lecture
q Introduction
q Two-stage Op-Amp Compensation
q Multi-stage Op-Amp Design
q Multi-stage Fully-Differential Op-Amps
q Conclusion
IEEE Solid-State Circuits Society – Gonzaga, April 9-10, 2015 2
Op-Amps and CMOS Scaling
Distinguished Lecture
q The Operational Amplifier (op-amp) is a fundamental building
block in Mixed Signal design.
ü  Employed profusely in data converters, filters, sensors, drivers etc.
q Continued scaling in CMOS technology has been challenging
the established paradigms for op-amp design.
q With downscaling in channel length (L)
ü  Transition frequency increases (more speed).
ü  Open-loop gain reduces (lower gains).
ü  Supply voltage is scaled down (lower headroom) [1].
IEEE Solid-State Circuits Society – Gonzaga, April 9-10, 2015 3
CMOS Scaling Trends
Distinguished Lecture
q VDD is scaling down but V is almost constant.
THN
ü  Design headroom is shrinking faster.
q Transistor open-loop gain is dropping (~10’s in nano-CMOS)
ü  Results in lower op-amp open-loop gain. But we need gain!
q Random offsets due to device mismatches.

[3], [4].
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Integration of Analog into Nano-CMOS?
Distinguished Lecture
q Design low-VDD op-amps.
ü  Replace vertical stacking (cascoding) by horizontal cascading of gain
stages (see the next slide).
q Explore more effective op-amp compensation techniques.
q Offset tolerant designs.
q Also minimize power and layout area to keep up with the
digital trend.
q Better power supply noise rejection (PSRR).

IEEE Solid-State Circuits Society – Gonzaga, April 9-10, 2015 5
Cascoding vs Cascading in Op-Amps
Distinguished Lecture
A Telescopic Two-stage Op-Amp
A Cascade of low-VDD
Amplifier Blocks.
(Compensation not shown here)
VDD VDD VDD VDD VDD VDD
VDD
2 n-1
1
vm vp n vout
CL
Vbiasn Vbiasn Vbiasn
Stage 1 Stage 2 Stage (n-1) Stage n
VDD >4V +V +V with
min ovn ovp THP VDD =2V +V +V
min ovn ovp THP.
wide-swing biasing. [1]

q  Even if we employ wide-swing biasing for low-voltage designs, three- or
higher stage op-amps will be indispensable in realizing large open-loop DC
gain.
IEEE Solid-State Circuits Society – Gonzaga, April 9-10, 2015 6
Distinguished Lecture
TWO-STAGE OP-AMP COMPENSATION
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Direct (or Miller) Compensation
Distinguished Lecture
q  Compensation capacitor (C )
c
VDD VDD
between the output of the gain stages
VDD
causes pole-splitting and achieves
M3 M4 M7
1 dominant pole compensation.
220/2
750Ω
v v i q  An RHP zero exists at
m p Cfb v
M1 M2 out
ü  Due to feed-forward component of
C
C
i 10pF 2 L
C C the compensation current (i ).
ff 30pF
C
V
bias3 q  The second pole is located at
M6TL 100/2
M6TR M8T
V
M6BL bias4 100/2 q  The unity-gain frequency is
M6BR M8B
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2. x10

v All the op-amps presented have been designed in AMI C5N 0.5µm CMOS process with scale=0.3 µm and L =2.
min
The op-amps drive a 30pF off-chip load offered by the test-setup.
IEEE Solid-State Circuits Society – Gonzaga, April 9-10, 2015 8
Drawbacks of Direct (Miller) Compensation
Distinguished Lecture
q  The RHP zero decreases phase
VDD VDD
VDD margin
M3 M4 M7 ü  Requires large C for
1
C
220/2
compensation (10pF here for a
30pF load!).
v v C
m p C v
M1 M2
out
C q  Slow-speed for a given load, C
2
10pF L L.
30pF
q  Poor PSRR
V
bias3
M6TL 100/2
M6TR M8T ü  Supply noise feeds to the output
V
M6BL bias4 100/2 through C .
M6BR M8B C
q  Large layout size.
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
x10
IEEE Solid-State Circuits Society – Gonzaga, April 9-10, 2015 9
Indirect Compensation
Distinguished Lecture
VDD VDD VDD q  The RHP zero can be eliminated by
VDD
blocking the feed-forward compensation
M3 M4 M9
1 M7 current component by using
220/2
ü  A common gate stage,
v
m i
M1 M2 c Cc
2 vout ü  A voltage buffer,
M
CG
v A CL
p ü  Common gate “embedded” in the
30pF
V
M6TL bias3 100/2 cascode diff-amp, or
M6TR M10T M8T
V
M6BL bias4 100/2 ü  A current mirror buffer.
M6BR M10B M8B
q  Now, the compensation current is fed-
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2. x10 back from the output to node-1 indirectly
through a low-Z node-A.
An indirect-compensated op-amp
using a common-gate stage. q  Since node-1 is not loaded by C , this
C
results in higher unity-gain frequency
(f ).
un
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