High Speed CMOS Design Styles

367 Pages·1999·27.257 MB·English

by  Kerry Bernstein, Keith M. Carrig, Christopher M. Durham, Patrick R. Hansen, David Hogenmiller, Edward J. Nowak, Norman J. Rohrer (auth.)

HIGH SPEED CMOS DESIGN STYLES
HIGH SPEED CMOS DESIGN STYLES
by
Kerry Bernstein
Keith M. Carrig
Christopher M. Durham
Patrick R. Hansen
David Hogenmiller
Edward J. Nowak
Norman J. Rohrer
IBM Microelectronics
~.
"
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
High speed CMOS design styles / Kerry Bemstein ... [et al.].
P. cm.
Includes bibliographical references and index.
ISBN 978-1-4613-7549-4 ISBN 978-1-4615-5573-5 (eBook)
DOI 10.1007/978-1-4615-5573-5
Metal oxide semiconductors, Complementary--Design and
construction. 2. Integrated circuits--Very large scale integration
-Design and construction. 3. Electronic circuit design.
1. Bemstein, Kerry, 1956-
TK7871.99.M44H54 1998
621.3815'2--dc21 98-28409
CIP
Copyright © 1999 by Springer Science+Business Media New York
Fifth Printing 2001.
Originally published by Kluwer Academic Publishers in 1999
Softcover reorint of the hardcover Ist edition 1999
AlI rights reserved. No~ part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Science+Business Media, LLC.
Printed on acid-free paper.
Prejace
Inresponsetotheneedforacompilationofhigh-speedCMOSconventionsandstruc
turesused inthemicroprocessordesigncommunity,thefollowingtextisoffered.
Emphasisisplacedonexaminingtheperformancevariabilityofthesestylescontrib
utedbyprocess,design, anduseconditions. Commentsarebasedontheauthors'
directexperienceinthe craftingand fabrication ofCMOSmicroprocessorsused in
highperformanceworkstationapplications. Iftheauthors haveaccomplishedtheir
goal,thetrade-offs inperformance,power, area,reliability, andcostmadebythe
selectionofdesignstylewill havebeenmadereadilyapparent.
Thetextisaimedatthegraduatelevelstudentorengineermainlyinterestedincircuit
design,andisintendedtoprovidesomepracticalreference,or"horse-sense"tomech
anismstypicallydescribedwithamoreacademicslant. Thisbookisorganizedsothat
itcanbeuSedasatextbookorasareferencework.
Chapter 1describessourcesofprocess-drivenperformancevariation in quarter
micronCMOS,andoffersrulesofthumbfordealingwiththem. Basicprocess
relateddesign considerationsare developed,andprovideabasisfordiscussion
throughouttherestofthe book. Whilethesetoleranceconceptsarenot limitedtoa
singlefabricatororprocess,thespecificationsforaparticularoperationoverridethe
roughrules ofthumbprovidedhere.
Chapter2surveysnon-clocked,staticcircuitfamilies usedto implementcombinato
rial logic. Theoperationofeachstyle,aswellas itsrespectivestrengthsandweak-
Preface
nessesareexplained. Uniquecharacteristicsandsensitivitiesareaddressed inmore
detail in the"Characteristics"subheadingforeach family.
Chapter3examinesclockedanddynamic logic. Featureswhich differentiateeach
stylefrom itsclockedandnon-clockedpredecessorsare identified. Becauseclocked
logicingeneralanddynamiclogicinparticularbringswithithigherdesign liabilities,
additional effortismadetodescribemechanismsknown tocreateheadaches.
Chapter4exploresdesign-drivenperformancevariabilityand, alongwiththeprocess
related variation, discussestheallocation ofdesign margin whichaccommodatesthe
compositedelaytolerance. Importanttopicssuch as on-chipdevice lengthtolerance,
noise, supplyrail inconsistencyandtemperature variationare integratedinthis chap
ter.
Variousstorageelementdesigns developedforhigh speedprocessorsarecoveredin
Chapter5. In Chapters2and3,numerous logiccircuitstructureswereshowntoexe
cute logicoperationsalongtheirpaths. Techniquesandstrategiescoveredin this
chapterusethemultiplelatchconfigurationsdescribedtofirst setupdatainputstobe
evaluated,andthento latercapturethe calculatedoutputs inan efficientmanner.
Anoverviewofpopularchip interface structuresandrelatedperformanceconsider
ationstosupporthighspeedchipcommunicationsisprovided inChapter6. Notonly
mustthecircuitconfigurationsenablehighspeedcommunication;theselected input/
outputconventionmustbecompatiblewiththesignal levelsanddesignstyleused
throughouttherestofthe chip.
Chapter7dealswiththemultiplicityofclockingstylesfound inthe industry.Thepre
viouschaptershintedatthe varietyofclockingstylesneededfortheoperationofspe
cificlogiccircuits,latches,andI/Odevicespreviousexplained. Inthischapter,weare
now fully introducedtothesignificanceofclockingchoice,and its profoundinflu
enceonperformance.
Twoimportantcontemporarytimingconcepts,slackborrowingandtimestealing,are
introducedinChapter8. Significantperformanceimplicationsareassociatedwith
howclockboundariesaredefined. Thesepracticesareonlymadepossiblebytheuse
ofnewerinnovativedesign styles,buildinguponthe latchingandclockingconcepts
developed inchapters 5, 6,and 7.
Finally, Chapter9updatesthereaderon emergingtechnologydirectionswhichare
likelytohaveasubstantial impactonfuturemicroprocessordesignstyles. Certain
devicedesign opportunitieswillenablecircuitconfigurationsnotpresently feasible.
vi HighSpeedCMOSDesignStyles
Thistextisnotintendedtobeacircuitdesignguide,noran authoritativereferencefor
thephysicsofVLSI. Rather,thisisasourceofgoodideasandacompilationofobser
vations,highlightinghow differentapproachestradeoffcriticalparameters indesign
andprocessspace. Ourindustry ismarkedbythecontributionsofmanyinnovative
people;someoftheirbestworksarereferencedwithin.Thereaderisdirectedtomore
focusedtextsandtothe citedreferencesformorethoroughtreatmentsofspecifictop
ics.
Theseareexcitingtimestobeinthisindustry.Thelimitstoscalingarenowbecoming
evident,makingtheneedforinnovationevenmoreurgent. Inasettingwherecompet
itorsall buyessentiallythesamefabrication toolsanddevelop quitesimilartechnolo
gies,whatdifferentiatesproductsfrom oneanotheristhelogicconfigurationselected,
andthecircuittopologiesusedtoimplementit. Adesignpointwhichmerelyperpetu
atesolddesignstylesin anewtechnology, usingexistingsynthesisandchecking
tools, isdoomedto, atbest,matchingthecompetitivedisposition itoccupiedinthe
priortechnology.Theselectiveintroductionofsuperiordesignstyleswithenlightened
technologyusage is imperativeforacompetitiveproduct.
Acknowledgments
Ifthistextissuccessfulinsharinginsightandexperience,itisdue in nosmallpartto
the legionofhighlyskilledanddedicatedemployeesthattheauthorshave beenhon
oredtoworkamongovertheyears.Althoughliterallyhundredsofpeoplehaveshared
theirinsightwith us, afew individualsmeritspecialrecognition.
Thisbookoriginatesfrom alecturepresentedatthe MITMTL VLSI Seminar. The
topicwascultivatedbyextendeddiscussionswith Dr. Larry Heller. Iam indebtedto
Larryforhis insight,generosity,andpatience. RonBlack,DirectorofIBMPowerPC
ProductDevelopment,recognizedtheneedfor atextwhich"tellsitlikeitis,"and
encouragedit'sdevelopment. Thejobofactuallycreatingsuchatextwouldhave
beenimpossiblewithoutthesupportandencouragementofSolLewin,IBMPowerPC
ChiefEngineer/Technologist. Thankyou, Sol. Wehavebenefittedfrom the valuable
inputofAndy Bryant,RobBusch,HowardChen,BillClark,JohnCohn,JohnCon
nors, DennisCox,EmmanuelCrabbe,JohnEllis-Monaghan,WesleyFavors, Frank
Ferraiolo, BillKlaasen,DianeKramer, MarkLasher, DavidLackey, Henry Levine,
StevenLuce,EdMaciejewski,TomMaffit,RobertMasleid,MichaelMaurice,Daniel
Menard,Glen Miles, SteveMittl, StevenOakland, TimO'Gorman,PhilipRestle,
JohnSheets,YuanTaur,XiaweiTian,BillVirun, SallyYankee,andJeffZimmerman.
loneMinotalwayshadafix forourpublishingsoftwaresnafus,andsomehow Bruce
Blackmankeptmakingcriticallyneededhardwaremagicallyappear.
Preface vii
Preface
Finally, Iam indebtedtomy co-authors, whomadetime inanalready heavily-com
mittedschedule,tojoinme in thisendeavor.
Kerry Bernstein
Underhill, Vermont
viii HighSpeedCMOSDesignStyles
This work is dedicated to our families, who kept the
fire going in the woodstove during this project; and to
ourprofessional mentors and peers, who unselfishly
share their experience and insight.
Contents
Preface v
CHAPTER 1 Process Variability 1
1.1 Introduction 1
1.1.1 Inter-Die Variations: Across-Lotand Across-Wafer
Variation 2
1.1.2 Intra-DieVariation 5
1.1.3 Fail Causes 5
1.2 Front-End-Of-LineVariability Considerations•....•6
1.2.1 ShortChannel Effectsand ACLV 6
1.2.2 NFET to PFET Length Tracking 10
1.2.3 Channel WidthEffects 11
1.2.4 Device ThresholdVoltageVariation 13
1.2.5 Mobile Charge 13
1.2.6 HotCarriers 15
1.2.7 DrainResistance Modulation 19
1.2.8 Negative Bias Temperature Instability (NBTI) 20
1.2.9 BodyEffect. 21
1.2.10 OtherProcess Parameters 22
1.3 ChargeLoss Mechanisms......•....•...........25
1.3.1 SubthresholdLeakage Currents 26
1.3.2 JunctionLeakage 27
1.3.3 Field-inducedLeakage Mechanisms 29
1.3.4 AlphaParticle andCosmic Ray Interactions 30
1.3.5 DefectLeakage 32
1.4 Back-End-Of-LineVariability Considerations 36
1.4.1 Wire Resistance 38
1.4.2 Line Width/Space 41
1.4.3 Dielectric Thickness and Pennittivity 43
1.4.4 Wire Thickness 44
1.4.5 ContactResistance 45
1.5 Summary 47
CHAPTER 2 Non-ClockedLogic Styles .....51
2.1 Introduction 51
2.2 StaticCMOS Structures....•.••...............•54
2.2.1 Static Combinatorial CMOS Logic 55
2.2.2 Pulsed Static Logic (PS-CMOS) 57
2.3 DCVS Logic 58
2.3.1 Differential Cascode Voltage-SwitchedLogic (DCYSL)59
2.3.2 Differential SplitLevel Logic (DSL) 61
2.3.3 CascodeNon-ThresholdLogic (CNTL) 63
2.3.4 DCYS CircuitFamilyProcess Sensitivities 64
2.4 Non-Clocked Pass-Gate Families................•65
2.4.1 CMOS Pass Gate (PG) andTransmission Gate (TG) .
Logic 68
2.4.2 DCYS Logic with the Pass Gate (DCYSPG) 71
2.4.3 ComplementaryPass Gate Logic (CPL) 73
2.4.4 Swing-RestoredPass Gate Logic (SRPL) 76
2.4.5 Energy-EconomizedPass TransistorLogic (EEPL) 78
2.4.6 Push-pull Pass transistor Logic (PPL) 79
2.4.7 Single-EndedPass-Gate Logic (LEAP) _..81
2.4.8 Double Pass-TransistorLogic (DPL) 84
2.4.9 Pass-Gate CircuitFamilyProcess Sensitivities 85
2.5 Summary ....... ..... ..... . . 86
xii HighSpeedCMOSDesignStyles