High-Speed Clock Network Design

190 Pages·2003·7.566 MB·English

by  Qing K. Zhu (auth.)

HIGH-SPEED CLOCK NETWORK DESIGN
High-Speed Clock Network
Design
by
QingK.Zhu
Intel Corporation, T-RAM Inc., U.S.A.
SPRINGER-SCIENCE+BUSINESS MEDIA, B.V.
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-5336-0 ISBN 978-1-4757-3705-9 (eBook)
DOI 10.1007/978-1-4757-3705-9
Printed on acid-free paper
All Rights Reserved
© 2003 Springer Science+Business Media Dordrecht
Originally published by Kluwer Academic Publishers in 2003
Softcover reprint ofthe hardcover 1st edition 2003
No part of this work may be reproduced, stored in a retrieval system, or transmitted
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Table of Contents
PREFACE ......................................................................................................... VI"I
CHAPTER 1 INTRODUCTION ................................................................. 1
1.1 CLOCK FREQUENCY AND POWER CONSUMPTION ....................................... 1
1.2 SOURCES OF CLOCK SKEW AND CLOCK JITTER .......................................... 2
1.3 ON-DIE VARIATIONS AND CLOCK SKEW IMPACTS ..................................... 6
1.4 CLOCK BUFFER CIRCUIT DESIGN ............................................................. 11
1.5 POWER SUPPLY AND RELIABILITY ISSUES ................................................ 17
1.6 DESIGN COMPLEXITY OF CLOCK DISTRffiUTION ....................................... 18
1.7 SUMMARY ............................................................................................... 22
CHAPTER 2 OVERVIEW TO TIMING CONSTRAINTS •••••••••••••••••••• 23
2.1 PROPAGATION DELAY ANDTRANSmoNTIME ......................................... 23
2.2 SETUP TIME CONSTRAINT ........................................................................ 24
2.3 HOlD TIME CONSTRAINT ......................................................................... 25
2.4 RECOVERY TIME AND PuLsE WIDTH ....................................................... 26
2.5 TIME BORROWING ................................................................................... 27
2.6 ONE EXAMPLE: FIxING HOlD TIME VIOLATIONS ..................................... 31
2. 7 DELAY SLACK GRAPH FOR TIMING CONSTRAINTS ................................... 37
2.8 SUMMARY ............................................................................................... 38
CHAPTER 3 SEQUENTIAL CLOCKED ELEMENTS ......................... 41
3.1 LATCH CLOCKING .................................................................................... 41
3.2 FLIP-FLop CLOCKING ............................................................................... 48
3.3 POWER REDUCTION ................................................................................. 53
3.4 SUMMARY ............................................................................................... 55
CHAPTER 4 DESIGN METHODOLOGY FOR DOMINO CIRCUITS• •• 57
4.1 DOMINO CIRCUIT TYPES .......................................................................... 57
4.2 CLOCK DISTRffiUTION FOR DOMINO CIRCUITS ......................................... 63
4.3 DESIGN OPTIMIZATION IN DOMINO CIRCUITS ........................................... 66
4.4 Low-VT DEVICES FOR DoMINO CIRCUITS ............................................... 68
4.5 SUMMARY ............................................................................................... 73
CHAPTERS CLOCK GENERATION AND DE-SKEWING• ••••••••••••••• 75
5.1 ON-CHIP CLOCK GENERATION ................................................................. 75
5.2 CHARACTERIZATION OF CLOCK GENERATOR ........................................... 78
5.3 LAYOUT GUIDELINES ............................................................................... 79
5.4 DE-SKEWING CIRCUITS ............................................................................ 81
5.5 CLOCK SHRINKING TECHNIQUE FOR SILICON DEBUG. .............................. 86
5.6 SUMMARY ............................................................................................... 88
v
CHAPTER 6 MICROPROCESSOR CLOCK DISTRIBUTION
EXAMPLES ....................................................................................................... 89
6.1 INTELIA-64 ............................................................................................. 89
6.2 INTEL PENTIuM IV ................................................................................... 93
6.3 INTEL PENTIuM ill .................................................................................. 99
6.4 DEC ALPHA ........................................................................................... 100
6.5 IBM POWERPC ...................................................................................... 103
6.6 SUMMARy ............................................................................................. 105
CHAPTER 7 CLOCK NETWORK SIMULATION MEmODS •••••••• I09
7.1 RCExlRACTION .................................................................................... 109
7.2 FuLL-CHIP CLOCK TREE TRACING ......................................................... 114
7.3 CLOCK TREE SIMULATION AND REPoRT FILEs ....................................... 114
7.4 IRDROpEFFECTS .................................................................................. 119
7.5 SUMMARy ............................................................................................. 123
CHAPTERS LOW-VOLTAGE SWING CLOCK DISTRIBUTION .. 125
8.1 1I2VDD SWING LocAL CLOCK DISTRffiunON ....................................... 125
8.2 Low VOLTAGE SWING GLOBAL CLOCK DISTRffiunON .......................... 128
8.3 SUMMARY ............................................................................................. 133
CHAPTER 9 ROUTING CLOCK ON PACKAGE ............................... 135
9.1 SCHEME OVERVIEW ............................................................................... 135
9.2 ESD DESIGN .......................................................................................... 137
9.3 TRANSMISSION LINE NOISE ON PACKAGE .............................................. 141
9.4 MICROPROCESSOR EXPERIMENTAL RESULTS ......................................... 142
9.5 SUMMARY ............................................................................................. 145
CHAPTER 10 BALANCED CLOCK ROUTING ALGORImMS .......... 147
10.1 PLANAR EQUAL PATH LENGTH CLOCK ROUTING ................................... 147
10.2 GEOMETRICALEMBEDDING ................................................................... 152
10.3 SKEW-BOUNDED REFINEMENT .............................................................. 153
10.4 WIRE SIZING OF CLOCK NETWORK ........................................................ 157
10.5 SUMMARY ............................................................................................. 161
CHAPTER 11 CLOCK TREE DESIGN FLOW IN ASIC ................... 163
11.1 FLow OVERVIEW ................................................................................... 163
11.2 GATED CLOCK TREE SYNTHESIS ............................................................ 166
11.3 CLOCK SKEW AND ToPOLOGY REPoRTS ................................................ 167
11.4 ROUTE THE CLOCK NET ......................................................................... 168
11.5 VERIFY THE CLOCK SKEW ..................................................................... 169
11.6 SUMMARY ............................................................................................. 170
GLOSSARY ...................................................................................................... 171
REFERENCE ................................................................................................... 177
IN'DEX ..•..............................•.......••..•....•.•..........................................•............... 186
vi
Preface
The author would like to thank: Mr. Mark D. Jongh at Kluwer
Academic Publishers for giving the opportunity to publish this book. He
also appreciates the help from Peter Chau and Huiling Song for their
reviewing and encouragements during the book writing.
This book is a collection of design concepts, techniques and
research works from the author for clock distribution in microprocessors
and high-performance chips. It is organized in 11 chapters as follows.
Chapter 1 provides an overview to the design of clock networks. Chapter
2 specifies the timing requirements in digital design. Chapter 3 shows the
circuits of sequential elements including latches and flip-flops. Chapter 4
describes the domino circuits, which need special clock signals. Chapter 5
discusses the phase-locked loop (PLL) and delay-locked loop (DLL),
which provide the clock generation and de-skewing for the on-chip clock
distribution. Chapter 6 summarizes the clock distribution techniques
published in the state-of-the-art microprocessor chips. Chapter 7 describes
the CAD flow on the clock network simulation. Chapter 8 gives the
research work on low-voltage swing clock distribution. Chapter 9
explores the possibility of placing the global clock tree on the package
layers. Chapter 10 shows the algorithms of balanced clock routing and
wire sizing for the skew minimization. Chapter 11 shows a commercial
CAD tool that deals with clock tree synthesis in the ASIC design flow.
The glossary is attached at the end of this book. The clock network design
is still a challenging task in most high-speed VLSI chips, since the clock
frequency and power consumption requirements are increasingly difficult
to meet for mUltiple clock networks on the chip. Many research works and
industry examples will be shown in this area to continually improve the
clock distribution networks for future high-performance chips.
vii
Chapter 1 Introduction
Clock distribution is one of the limiting factors for the high
frequency chip design. Device technology improvement, such as deep
submicron with faster transistors, can only marginally solve the clock
distribution problem because the interconnect delay becomes the
significant factor in the clock cycle time. Section 1.1 provides the
introduction to clock frequency and power issues. Section 1.2 explains the
sources of the clock skew and clock jitter, which are two major design
issues in the clock network design. Section 1.3 shows the PVT effects on
the clock skew. Section 1.4 describes the clock buffer design. Section 1.5
discusses the power supply and reliability for clock distribution. Section
1.6 demonstrates the design complexity of the clock distribution network
by using a microprocessor example. Section 1.7 provides the summary to
this chapter.
1.1 Clock Frequency and Power Consumption
Figure l-l(a) and Figure l-l(b) show the trends of interconnect
delay versus gate intrinsic delay and microprocessor clock frequency. A
clock frequency has been achieved at 2.5GHz in Intel Pentium-N chips.
Chip technology improvement such as smaller feature size, larger chip
area, and increased component density are increasing the difficulties of
the clock distribution, since they usually result in higher series
interconnect resistance and higher clock loads.
Insertion of multiple intermediate levels of clock buffers helps in
the transition time and power reduction for the clock tree. But it cannot
resolve the clock skew problem, because the clock skew is caused by the
process variations in the clock buffers. Extensive research has been
performed on the RC delay balance by equating the delay along the
branches of the clock tree. H-tree design is widely used in the industry
for achieving the equal path lengths based on the recursive H tree
structure [2,3]. mM's Power-PC and DEC's Alpha microprocessor chips
both use the H-tree design for global clock distribution [4,5]. A limitation
of the H-tree is that the clock sinks should be placed in symmetric or
Q. K. Zhu, High-Speed Clock Network Design
© Springer Science+Business Media Dordrecht 2003
Chapter 1 Introduction
uniform locations. Clock grids or clock trunks are also used in the
industry with the penalty of taking a large wiring area and causing much
more load capacitances [6]. Balanced clock tree construction algorithms
for the arbitrary locations of clock sinks (to eliminate the H-tree
limitation) can be found in academic research works by Jackson and Kuh
(Method of Means and Medians) [7], Kahng, Cong, and Robins
(Recursive Geometric Matching Method) [8], Tsay (Elmore Delay
Matching Method) [9], Chao, Hsu, Ho, Edahiro, Boese, and Kahng
(Deferred-Merge Embedding Methods) [10,11,12], Chou and Cheng
(Simulated Annealing Method) [13], Zhu, Dai, Kahng, and Tsao (Planar
Equal Path Length Clock Tree Methods) [14,15,16].
Not only is skew an important consideration when designing a
clock network, but other factors must be taken into account as well. For
instance, clock rise and fall time is proportional to both line resistance
and load capacitance, so it is desirable to reduce both of these
characteristics. References [24-25] discussed the statistical models for IC
chip circuit simulation. Reference [26] considered the delay matching of
two clock buffers in pull-up and pull-down edges with process variations.
References [27-29] considered the process variations in clock buffer
sizing and wire sizing. Reference [30] showed the general principles
behind the clock buffer delay and size optimization. Reference [31]
showed an analytic way to determine the clock buffer size.
In order to reduce the power consumption, it is useful to adopt the
clock gating whenever possible in the clock distribution network. In
addition, reducing gate and line capacitances of the clock network will
help the power reduction. The clock network itself may take up to 50% of
the chip total power consumption, as illustrated in Figure 1-2, based on
the data from Intel.
1.2 Sources of Clock Skew and Clock Jitter
With increasing clock frequency, clock inaccuracy has become a
large percentage of the clock period. It is critical that one accounts for the
clock inaccuracy in the minimum and maximum path delay calculations.
The clock inaccuracy is basically a spatial and temporal phenomenon,
causing one clock edge not to arrive at a sampling point at its nominal
time, measured relative to another clock edge. The clock inaccuracy
consists of two components: the clock skew and the clock jitter. Clock
skew represents the spatial separation effect of the clock inaccuracy,
whereas clock jitter represents the temporal separation effects of the clock
2
High-Speed Clock Network Design
inaccuracy. Figure 1-3 illustrates the clock skew that is the path delay
difference of clock signals from the common clock root (the output of the
on-chip phase-locked loop) to two clocked elements. The clocked
elements can be the latch, flip-flop, domino circuit, etc. There are
systematic and random effects that contribute to the clock skew as follows
[58]:
• Variations in effective channel lengths of devices across the die.
This is caused by global in-die variations resulting from lens
distortions, wafer planarity, stepper accuracy etc. Also local
effects like device proximity and some other random phenomena
(e.g. dopant infiltration of the channel) result in channel length
variations.
• Threshold voltage Vt variation across the dieWider devices has
smaller variations in Vt compared to narrower devices. Typical
variation could be as high as 50mV for narrow devices.
• Inter-layer dielectric (ILD) thickness variation. This causes the
interconnect capacitance to vary, resulting in delay variation in
interconnect dominated paths.
• Design errors. These arise from human errors like mistakes in
modelling the circuit, choice of simulation step size, etc., and
from the tool related errors in RC parasitic extraction, simulator
accuracy, etc.
• Supply voltage variation across the die. This depends on power
grid design, proximity to high activity and large devices, etc.
• Temperature difference across the die. It is very likely to have 5-
100C across a microprocessor chip.
• Signal coupling to neighbouring lines. One path may be highly
coupled to neighbouring lines compared to another, causing the
clock skew between two paths.
3
Chapter 1 Introduction
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4