High Speed and Wide Bandwidth Delta-Sigma ADCs

133 Pages·2014·0.96 MB·English

by  Muhammed Bolatkale

ACSP · Analog Circuits And Signal Processing
Muhammed Bolatkale
Lucien J. Breems
Kofi A.A. Makinwa
High Speed
and Wide
Bandwidth
Delta-Sigma
ADCs
Analog Circuits and Signal Processing
SeriesEditors:
MohammedIsmail.TheOhioStateUniversity
MohamadSawan.ÉcolePolytechniquedeMontréal
Forfurthervolumes:
http://www.springer.com/series/7381

Muhammed Bolatkale (cid:129) Lucien J. Breems
Kofi A.A. Makinwa
High Speed and Wide
Bandwidth Delta-Sigma
ADCs
123
MuhammedBolatkale LucienJ.Breems
NXPSemiconductors NXPSemiconductors
Eindhoven,TheNetherlands Eindhoven,TheNetherlands
KofiA.A.Makinwa
DelftUniversityofTechnology
Delft,TheNetherlands
ISSN1872-082X ISSN2197-1854(electronic)
ISBN978-3-319-05839-9 ISBN978-3-319-05840-5(eBook)
DOI10.1007/978-3-319-05840-5
SpringerChamHeidelbergNewYorkDordrechtLondon
LibraryofCongressControlNumber:2014935880
©SpringerInternationalPublishingSwitzerland2014
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Contents
1 Introduction .................................................................. 1
1.1 TrendsinWideBandwidthandHighDynamicRangeADCs........ 3
1.2 MotivationandObjectives.............................................. 4
1.3 OrganizationoftheBook............................................... 5
References..................................................................... 6
2 Continuous-TimeDelta-SigmaModulator................................ 9
2.1 IdealDelta-SigmaModulator........................................... 9
2.1.1 SystemOverview............................................... 9
2.1.2 Quantizer........................................................ 12
2.1.3 DAC............................................................. 15
2.1.4 LoopFilter ...................................................... 16
2.2 System-LevelNon-idealities ........................................... 19
2.2.1 Noise ............................................................ 20
2.2.2 Non-linearity.................................................... 22
2.2.3 ExcessLoopDelay ............................................. 24
2.2.4 Metastability .................................................... 30
2.3 Summary ................................................................ 33
References..................................................................... 34
3 Continuous-Time Delta-Sigma Modulators at High
SamplingRates............................................................... 37
3.1 System-LevelDesign ................................................... 37
3.1.1 CT(cid:2)†ModulatorDesignatHighSamplingRates........... 37
3.1.2 ExcessLoopDelayCompensationwithanActive
Amplifier........................................................ 40
3.1.3 High-SpeedCapacitiveFeedforwardCT(cid:2)†Modulator..... 46
3.2 Block-LevelDesignRequirements..................................... 50
3.2.1 LoopFilter ...................................................... 51
3.2.2 Quantizer........................................................ 57
3.2.3 FeedbackDAC(DAC1) ........................................ 64
3.2.4 QuantizerDAC(DAC2)........................................ 68
v
vi Contents
3.3 Conclusions ............................................................. 70
References..................................................................... 71
4 A4GHzContinuous-Time(cid:2)†ADC...................................... 73
4.1 Introduction ............................................................. 73
4.2 ImplementationDetails................................................. 74
4.2.1 CT(cid:2)†ADCArchitecture...................................... 74
4.2.2 QuantizerDesignandTimingDiagramoftheModulator.... 75
4.2.3 FeedbackDACs................................................. 78
4.2.4 OperationalTransconductanceAmplifier...................... 80
4.2.5 DecimationFilter ............................................... 81
4.3 ExperimentalResults ................................................... 81
4.3.1 MeasurementSetup............................................. 81
4.3.2 MeasurementResults........................................... 82
4.4 Conclusions ............................................................. 92
References..................................................................... 92
5 A2GHzContinuous-Time(cid:2)†ADCwithDynamicError
Correction .................................................................... 95
5.1 Introduction ............................................................. 95
5.2 DynamicErrorCorrectionTechniquesin(cid:2)†Modulators........... 100
5.2.1 TheErrorSwitchingTechnique................................ 104
5.3 Multi-modeHigh-Speed(cid:2)†ADCDesign............................ 105
5.4 ImplementationDetails................................................. 108
5.4.1 InputStageandtheLoopFilter................................ 109
5.4.2 PulseGenerator................................................. 110
5.5 ExperimentalResults ................................................... 112
5.6 Conclusions ............................................................. 115
References..................................................................... 115
6 Conclusions................................................................... 117
6.1 Benchmarking........................................................... 118
6.2 FutureWork............................................................. 119
References..................................................................... 121
A ComparisonofADCArchitectures ........................................ 123
B Non-linearityofanIdealQuantizer ....................................... 127
References..................................................................... 128
Glossary........................................................................... 129
Index............................................................................... 131
Chapter 1
Introduction
Analog-to-digitalconverterdevelopmentsaredrivenbythe increasingdemandfor
signal bandwidth and dynamic range in applications such as medical imaging,
high-definitionvideo processing and, in particular, wireline and wireless commu-
nications. Figure 1.1 shows a block diagram of a basic wireless receiver. It has
threemainbuildingblocks:anRFfront-end,ananalog-to-digitalconverter(ADC)
anda digitalbasebandprocessor. Therole of the RF front-endis to filter, amplify
the signals present at the antenna input and down-convertthem to baseband. The
ADC samples and digitizes the analog signals at the output of the RF front-
end and outputs the results to the baseband processor. To achieve high data
rates, wireless standards rely on advanced digital modulation techniques that can
be advantageously implemented in baseband processors fabricated in nanometer-
CMOS,whichalsomotivatesthedevelopmentofADCsinthesetechnologies.
InmodernwirelessapplicationssuchasdigitalFMandLTE-advanced,theADC
receivesasignalwhosebandwidthcanbeaslargeas100MHz[1–3].Awideband
ADCwhichcancapturesuchsignalssimplifiesthedesignoftheRFfront-end,since
the channel selection filters can then be implemented in the baseband processor.
However, due to the limited filtering characteristic of the RF front-end, large
unwantedsignals(blockers)areoftenpresentattheinputoftheADC.Therefore,the
ADC shouldhave a high dynamicrange,oftenmore than 70dB. Wide bandwidth
and high dynamic range (DR) are thus importantattributes of ADCs intended for
highdata-ratenext-generationwirelessapplications.
Practically,NyquistADCshavebeenpreferredforapplicationswhichtargetwide
bandwidth, since the sampling frequency (f ) only has to be slightly higher than
s
2 (cid:2) BW, where BW is the bandwidth of the desired signal. A plot of dynamic
range vs. bandwidthfor variousstate-of-the-artADCs with energy efficiency less
than 1pJ/conv.-step. is shown in Fig.1.2. As can be seen, many Nyquist ADCs
achieve both wide bandwidths and high DR. A Nyquist ADC requires an input
sampling circuit which is often implemented with a switched-capacitor network.
AchievinghighDR,thenrequireslowthermalnoise,whichinturn,leadstoalarge
M.Bolatkaleetal.,HighSpeedandWideBandwidthDelta-SigmaADCs,AnalogCircuits 1
andSignalProcessing,DOI10.1007/978-3-319-05840-5__1,
©SpringerInternationalPublishingSwitzerland2014
2 1 Introduction
Antenna
RF X(t) Y(n) Baseband Data
ADC
Front end Processor Out
f f
s s
Fig.1.1 Abasicblockdiagramofawirelessreceiver
100
Nyquist ADC
90 Delta-Sigma ADC
Delta-Sigma ADC - ISSCC 2012
80
B)
d
e ( 70 This work [4]
g
an 60
R
c
mi 50
a
n
y 40
D
30
20
0 10 20 30 40 50 60 70 80 90 100110120130140150160
Bandwidth (MHz)
Fig.1.2 Dynamicrangevs.bandwidthofstate-of-the-art ADCswithpowerefficiencylessthan
1pJ/conv.-step.ThehighspeedCT(cid:2)†ADCsimplementedinnm-CMOSthathaverecentlygained
popularityareincludedtoemphasizethedevelopmentsinoversampledconverters[5]
inputcapacitance.However,thismustbeprecededbyananti-aliasingfilterandan
inputbuffercapableofdrivingalargecapacitance,whichincreasesthecomplexity
andpoweroftheRFfront-end.
Oversampledconvertersareverywellsuitedforapplicationswhichrequirehigh
dynamic range. In particular,a delta-sigma modulator ((cid:2)†M), which trades time
resolution for amplitude resolution, can achieve a high dynamic range with very
goodpowerefficiency(Fig.1.2).The(cid:2)†Misoneofthemostpromisingconverter
architectures for exploiting the speed advantage of CMOS process technology.
However,achievingawidebandwidthwitha(cid:2)†Mrequiresahigh-speedsampling
frequency due to the large OSR (f D 2 (cid:2) OSR (cid:2) BW, where OSR is the
s
oversamplingratio). The stability and power efficiencyof the modulatorat a high
sampling rate, together with achieving a high dynamic range at the low supply
voltages required by the nanometer-CMOS fabrication process, are important
challengesthatfacethenextgenerationofoversampledconverters.
1.1 TrendsinWideBandwidthandHighDynamicRangeADCs 3
This book focuses on the design of wide-bandwidth and high dynamic range
(cid:2)†Ms that can bridge the bandwidth gap between Nyquist and oversampled
converters.Morespecifically,thisbookdescribesthestability,thepowerefficiency
andthelinearitylimitsof(cid:2)†MsaimingataGHzsamplingfrequency.
1.1 Trendsin WideBandwidthandHighDynamic
RangeADCs
As shown in Fig.1.2, Nyquist ADCs based on the pipeline architecture have
achievedsamplingspeedsofupto125MHzanddynamicrangesgreaterthan70dB
in standard CMOS [6–8]. To achieve higher sampling rates, a Bi-CMOS or SiGe
Bi-CMOSprocesscanbeusedatthecostofhigherpowerconsumptionduetotheir
highersupplyvoltages(1.8–3.0V)[9,10].AfurtherdrawbackofpipelineADCsis
that they typically rely on high-gain wideband residue amplifiers and/or complex
calibration techniques to reduce gain errors [7–9], thus increasing their area and
complexity.
Recently,NyquistADCsbasedonthesuccessiveapproximationregister(SAR)
architecturehaveachievedsignalbandwidthsofup to 50MHz with 56–65dBDR
andexcellentpowerefficiency(<80fJ/conv.-step)[11–14].Greaterbandwidthcan
be achievedby using time-interleaving.However,the linearity of time-interleaved
SAR ADCs is limited by gain, offset, and timing errors and so such ADCs also
require extensive calibration [15]. Furthermore, time interleaving increases input
capacitanceandchiparea,andthusplacesmoredemandsontheinputbuffer[16].
Bycontrast,CT(cid:2)†ADCscanhaveasimpleresistiveinputthatdoesnotrequire
theuseofapower-hungryinputbufferorananti-aliasingfilter,whichfurtherrelaxes
the requirements of the RF front-end. When implemented in CMOS, such ADCs
haveachievedsignalbandwidthsofupto25MHzwitha70–80dBdynamicrange
andgoodpowerefficiency(<350fJ/conv.-step)[17–19].TypicalCT(cid:2)†modulators
employ a high-order loop filter with a multi-bit quantizer, which, for a 20MHz
bandwidth,requiresamplingfrequenciesof0.5–1GHztoachievemorethan70dB
of dynamic range. Assuming that the sampling frequency is proportional to the
bandwidth, sampling frequencies of 2.5–5GHz will be then required to achieve
bandwidthsgreaterthan100MHz.However,atGHzsamplingrates,parasiticpoles
andquantizerlatencycaneasilycausemodulatorinstability.
CT(cid:2)† modulatorswith signalbandwidthsup to 20–25MHz havebeen imple-
mentedin90–130nmCMOS.TheswitchingspeedofanNMOStransistorin45nm
CMOS isapproximately1.6(cid:2)faster thanin 90nm CMOS and2.7(cid:2)faster thanin
130nm CMOS[20]. Implementing a (cid:2)† modulator in 45nm LP CMOS is thus
advantageous for circuits such as quantizers and DACs whose delay is important
for stability. However, the dynamic range of circuits in 45nm CMOS is limited
by the low intrinsic gain and poor matching of the transistors [21,22]. The low
operatingsupply(1.1–1.0V)furthermoreimpliesthatcascadedstagesarerequired