High-Level Synthesis Blue Book

286 Pages·11.243 MB·English

by  Fingeroff M.

High-Level Synthesis
Blue Book
While the publisher and author have used their best efforts in preparing this book, they make
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of this book, and specifically (i) disclaim any implied warranties of merchantability or fitness
for any specific purpose, and (ii) assume no responsibility or liability for the contents of this
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ten sales materials. The publisher and author caution that the advice and strategies contained
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indirectly from the use of this book or the information contained herein.
© 2010 Mentor Graphics Corporation
All Rights Reserved
“You can't always get what you want
But if you try sometimes you just might find
You get what you need “
The Rolling Stones

Preface
As a former RTL designer who made the switch to High-Level Synthesis (HLS) years ago, I can
still remember both the excitement of discovering a totally new design methodology, as well as
the frustration of not knowing what to expect from the HLS tool as I attempted to code increas-
ingly complex designs.
My first exposure to the world of HLS began with a demo of a FIR filter written in C++, and syn-
thesized directly to RTL. This was a design I was very familiar with coming from the world of
RTL. After having written numerous hand-coded VHDL and Verilog implementations, I was
completely blown away when I saw how a single algorithmic C++ description could be used to
generate a large number of RTL implementations, each with different area/performance character-
istics. The HLS tool was able to do in a matter of minutes, what normally would take me days or
weeks to accomplish. The fact that it was then able to take the resulting RTL and simulate it using
my C++ testbench to prove functionality was simply unbelievable. The potential of the technol-
ogy was too attractive for me not to make the switch, and I soon found myself working in the field
of HLS.
As I began to tackle more complex designs, I started to encounter occasional problems with
achieving the best possible results. What I saw was that the style in which my C++ was written
could have a big impact on the resulting quality of the RTL. I would liken this to what I had expe-
rienced when people were first making the switch from schematic based design to RTL, where
proper coding style was critical to good quality of results. Fortunately for me, I was working with
a number of experts in HLS who I could rely on to provide the explanation as to why a particular
coding style gave less than desirable results, and who could suggest a better way to write the C++.
I was lucky since at that time there was no formal style guide for writing C++ for synthesis.
As HLS has matured the quality of results has improved dramatically for a much wider range of
C++ coding styles. However, this does not mean that all styles are equal, and there is still the
potential for ending up with poor quality RTL when the C++ is not well written. Good style not
only requires an understanding of the underlying hardware architecture of an algorithm, so that it
is reflected in the C++ design, but also an understanding of how HLS works.
This book presents the recommended coding style for C++ synthesis that results in good quality
RTL. Most of the C++ examples are accompanied with hardware and timing diagrams, where
appropriate. The basic concepts of HLS are introduced and an effort is made to relate them
directly to concepts that are well understood by RTL engineers. Although this book focuses pri-
marily on C and C++ to illustrate the fundamentals of C++ synthesis, all concepts presented here
are equally applicable to SystemC when describing the core algorithmic part of a design.
Although the examples are simplistic in many cases, they illustrate the fundamental principles
behind C++ hardware design. These concepts will translate to much larger designs.
As a final thought for the RTL Designers, System Architects, and Algorithm Designers who are
looking to adopt High-Level Synthesis; correct-by-construction RTL synthesized from C++ may
not look exactly like what you would code by hand. HLS optimizations often can result in the odd
v
logic gate in the resulting schematic. The hardware diagrams in this book exclude all of the extra-
neous logic. You will probably end up saying at some point that “It’s not exactly what I expected
the RTL to look like”. However you should also ask yourself “How long would it have taken to
write using hand-coded RTL?”, “Would it have simulated correctly the first time?” and ultimately
“Is it good enough?”. If you don’t get too caught up in the details you’ll find the results to be
exactly what you need.
Mike Fingeroff, January 2010
Who Should Read This Book
Engineering managers should read chapter one to understand how HLS evolved from existing
design methodologies and how it can help improve current design flows. RTL designers should
read the entire book and System/Algorithm designers should read chapters 3, 4, 5, 8, and 9, at the
very least.
About the Authors
Mike Fingeroff has worked as a technical marketing engineer for the Catapult C product line at
Mentor Graphics since 2002. His area of interests includes DSP and high-performance video
hardware. Prior to working for Mentor Graphics he worked as a hardware design engineer devel-
oping real-time broadband video systems. Mike Fingeroff received both his bachelors and masters
degrees in electrical engineering from Temple University in 1990 and 1995 respectively.
Thomas Bollaert is product marketing manager for the Catapult C product line at Mentor Graph-
ics. He has a more than 15 years of experience in EDA, and an extensive background in system-
level design and high-level synthesis. More recently, Thomas worked in tight collaboration with
Mentor Graphics’ European customers, helping them learn, adopt and deploy high-level synthesis
to improve their design practices. He earned his electronic engineering degree from ESIEE Paris
where he specialized in hardware architectures for signal processing applications.
vi
Acknowledgements
I would like to thank all of the people that contributed to the creation of this book by taking their
valuable time to review the content and provided essential feedback.
Emmanuel Liegeon, Thales Alenia Space
Mathieu Lebon, Alyotech
Katsunobu Natori, Hitachi Ltd.
Special thanks to Shawn McCloud, the High-Level Synthesis Product Line Director at Mentor
Graphics, for providing me with the time and resources to write this book.

I would also like to thank all of my co-workers at Mentor Graphics for providing internal review
of the book: Suravinth Sundralingam, David Burnette, Tony Vandinh, Mike Bradley, Mike Hilsen,
and Bob Condon,
Lastly I would like to thank Thomas Bollaert for his contribution of the first chapter of this book
as well as his input on the cover artwork. Thanks to Lucien Murray-Pitts for both his review and
contribution to the technical content. Special thanks to Bryan Bowyer and Peter Gutberlet for
answering numerous questions about HLS and coding style. Thanks to Ron Plyler for his discus-
sion on pipeline feedback, and finally thanks to Andres Takach, Stuart Clubb, and Tom Nagler for
their contributions to the chapter on FFT transforms.
vii
viii
Table of Contents
Chapter 1
Making the Case for High-Level Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
A broken design flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Keeping up with the pace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits of high-level synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Reducing design and verification efforts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
More effective reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Investing R&D resources where it really matters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Seizing the opportunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 2
General C++ Style. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
File Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Building an Executable Using Makefiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Makefile Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Phony Targets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Simple Makefile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Header/Include Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Creating a Golden Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Make Sure You're Fully Testing the DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Uninitialized Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3
Bit Accurate Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Compilation, Debug, and Simulation Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Header Files and Typedefs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Integer Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unsigned integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Signed Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Fixed Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Unsigned Fixed Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Signed Fixed Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Quantization and Overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bitwise Arithmetic Operators: *, +, -, /, &, |, ^,% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bit Select Operator: []. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ix
Shift Operators: <<, >>. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Methods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Slice Read: slc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Helper/Utility Functions 33
Array Uninitialization: ac::init_array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ceil, floor, and nbits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Complex Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter 4
Fundamentals of High Level Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
The Top-level Design Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Registered Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Control Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
High-level C++ Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Flow Graph Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Resource Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Classic RISC Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Loop Pipelining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
What's in a Loop?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Rolled Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Loop Unrolling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Loops with Conditional Bounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Optimizing the Loop Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Optimizing the Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Sequential Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Pipeline Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Data Feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Control Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Functions and Multiple Conditional Returns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 5
Scheduling of IO and Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Unconditional IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Conditional IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
x