High-Efficiency Linear RF Power Amplifiers Development Nuttapong

135 Pages·2005·1.78 MB·English

High-Efficiency Linear
RF Power Amplifiers Development
A Dissertation
Presented to
The Academic Faculty
by
Nuttapong Srirattana
In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy
School of Electrical and Computer Engineering
Georgia Institute of Technology
11 April 2005
High-Efficiency Linear
RF Power Amplifiers Development
Approved by:
Dr. Phillip E. Allen, Advisor Dr. John Papapolymerou
College of Engineering College of Engineering
Georgia Institute of Technology Georgia Institute of Technology
Dr. Joy Laskar, Co-Advisor Dr. Ye Li
College of Engineering College of Engineering
Georgia Institute of Technology Georgia Institute of Technology
Dr. John D. Cressler Dr. Paul A. Kohl
College of Engineering College of Engineering
Georgia Institute of Technology Georgia Institute of Technology
Date Approved: April 11, 2005
To Noppawan, Chongrak, and Nuttapan Srirattana,
my beloved family.
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ACKNOWLEDGEMENTS
First of all, I would like to express my deepest gratitude to my advisors, Prof. Phillip
E. Allen and Prof. Joy Laskar, for granting me a wonderful opportunity to conduct
this interesting research and for their guidance and encouragement throughout the
work. I gratefully acknowledge Prof. John Cressler, Prof. John Papapolymerou,
Prof. Ye Li, and Prof. Paul Kohl for serving on my defense committee.
I would like to thank the members of Microwave Application Group, past and
present, for their assistance, cooperation, and encouragement. Special thanks are
given to Deukhyoun Heo and Arvind Raghavan for introducing me to RF power
amplifier design, to Hyun-Min Park for valuable discussions and help with measure-
ments, and to Sebastien Nuttinck, Chang-Ho Lee, Kyu-Tae Lim, Sang Woong Yoon,
Padmanava Sen, and Rajarshi Mukhopadhyay for collaborations in power amplifier
design and device modeling.
I would also like to thank National Semiconductor Corporation for giving me
an internship opportunity during 2001 and 2002. I would like to thank Vikram
Krishnamurthy (now with VT Silicon), Emery Chen, and Andy Mclean (National
Semiconductor Corporation) for the opportunity to work with them and for many
helpful discussions. I would like to thank Patrick O’Farrell and Arlo Aude (National
Semiconductor Corporation) for their help with circuit layout and submissions, and
Stan Halpern (Georgia Tech Research Institute) for help in wire-bonding. I would
also like to thank National Semiconductor Corporation and Samsung Electronic for
providing CMOS and SiGe BiCMOS processes used in this work.
My family has always given me strong support and encouragement in my studies
and in other aspects of my life. I would like to thank and express my deepest love to
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everyone in my family (Noppawan and Chongrak Srirattana, my parents, Nuttapan
Srirattana, my brother) from the bottom of my heart. Special thanks are also given
to Thidarat Tosukhowong for her love, support, understanding, and encouragement.
Finally, I would like to thank all my friends for supporting and encouraging me
throughout my stay at Georgia Tech.
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TABLE OF CONTENTS
DEDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . iv
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
CHAPTER 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . 1
1.1 The Need for High-Efficiency Linear RF
Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
CHAPTER 2 BASICS OF EFFICIENCY ENHANCEMENT TECH-
NIQUES IN RF POWER AMPLIFIERS . . . . . . . . . . . . . . . 7
2.1 Classes of Operation in RF Power
Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Efficiency Enhancement Techniques for RF Power Amplifiers . . . . 14
2.2.1 Envelope Elimination and Restoration . . . . . . . . . . . . . 15
2.2.2 Bias Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 Doherty Amplification Technique . . . . . . . . . . . . . . . . 17
2.2.4 Chireix’s Outphasing Technique . . . . . . . . . . . . . . . . 18
2.3 Basics of RF Power Amplifiers Design . . . . . . . . . . . . . . . . . 19
2.3.1 Transistor Modeling . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Load-pull Measurement Techniques . . . . . . . . . . . . . . 21
2.3.3 Power Amplifier Design Considerations . . . . . . . . . . . . 24
CHAPTER 3 MULTISTAGE DOHERTY POWER AMPLIFIERS
DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Doherty Amplifier Technique . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Multistage Doherty Amplifier Technique:
Analysis and Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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3.2.1 Principle of Operation . . . . . . . . . . . . . . . . . . . . . . 32
3.2.2 Efficiency Calculation . . . . . . . . . . . . . . . . . . . . . . 37
3.3 Practical Considerations in Multistage
Doherty Amplifier Design . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
CHAPTER 4 LARGE-SIGNAL RF MOSFETS MODELING . . . 50
4.1 MOSFET Device Models . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Introduction to Modified-BSIM3v3 Model . . . . . . . . . . . . . . . 50
4.2.1 NQS Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.2 Distributed Gate Resistance . . . . . . . . . . . . . . . . . . 52
4.2.3 Distributed Substrate Resistance . . . . . . . . . . . . . . . . 53
4.3 Scalable Modified-BSIM3v3 MOSFET model . . . . . . . . . . . . . 56
4.3.1 Scalability of MOSFET model . . . . . . . . . . . . . . . . . 56
4.3.2 Extraction of Small-Signal Model Parameters . . . . . . . . . 58
4.3.3 Scalable Substrate Network Modeling . . . . . . . . . . . . . 66
4.3.4 Modified-BSIM3v3 Model . . . . . . . . . . . . . . . . . . . . 75
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CHAPTER 5 THE DESIGN OF INTEGRATED RF POWER AM-
PLIFIERS WITH THE DEVICE PERIPHERY ADJUSTMENT
TECHNIQUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.1 Motivation and Goal . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.2 Analysis of the Device Periphery Adjustment Technique . . . . . . . 89
5.3 1.9 GHz CMOS Power Amplifier Design . . . . . . . . . . . . . . . . 93
5.4 1.9 GHz CDMA/PCS SiGe HBT Power
Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.5 Nonlinear Terms Cancellation for Linearity Improvement . . . . . . 102
5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
CHAPTER 6 CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . 108
6.1 Contributions of the Dissertation . . . . . . . . . . . . . . . . . . . . 108
vii
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3 List of Publication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
VITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
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LIST OF TABLES
Table 1 Extracted intrinsic and substrate parameters of N-MOSFET devices
at V = 1.2 V; V = 2.4 V. . . . . . . . . . . . . . . . . . . . . . . 66
gs ds
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LIST OF FIGURES
Figure 1 The evolution of mobile communication systems. . . . . . . . . . . 2
Figure 2 Voltage and current waveforms of power amplifier in different classes
of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3 Class-D operation; (a) schematic diagram, (b) push-pull class-D am-
plifier, (c) voltage and current waveforms of class-D amplifier. . . . 10
Figure 4 Class-E operation; (a) schematic diagram of class-E amplifier, (b)
voltage and current waveforms of class-E amplifier. . . . . . . . . . 11
Figure 5 Class-F operation; (a) schematic diagram of class-F amplifier, (b)
voltage and current waveforms of class-F amplifier. . . . . . . . . . 13
Figure 6 Envelope Elimination and Restoration system; (a) system config-
uration, (b) implementation of the output stage by low-frequency
feedback amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7 Bias adaptation system. . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8 Doherty amplifier system configuration. . . . . . . . . . . . . . . . 17
Figure 9 Chireix’s Outphasing amplifier system. . . . . . . . . . . . . . . . . 18
Figure 10 Ideal dc load line for the calculation of optimum load. . . . . . . . 22
Figure 11 Load-pull system configuration. . . . . . . . . . . . . . . . . . . . . 23
Figure 12 Load-pull measurement result. . . . . . . . . . . . . . . . . . . . . . 24
Figure 13 Schematic diagram of the classical Doherty amplifier. . . . . . . . . 29
Figure 14 Drain efficiency of the classical Doherty amplifier. . . . . . . . . . . 31
Figure 15 Schematic diagram of the multistage Doherty amplifier. . . . . . . . 32
Figure 16 Equivalent circuit of the three-stage Doherty amplifier at (a) low-
power operation, (b) medium-power operation, (c) high-power oper-
ation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17 DrainefficiencyofthemultistageDohertypoweramplifier(DPA)us-
ing class-B amplifiers (γ = 2, γ = 4, γ = 4; γ = 4 for asymmetrical
1 2 3
DPA [25]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 18 Fundamental current as a function of conduction angle (A = relative
device periphery). . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 19 Schematic diagram of the three-stage WCDMA Doherty power am-
plifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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