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HBM3 JEDEC Spec PDF

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JEDEC STANDARD High Bandwidth Memory DRAM (HBM3) C E D E J JESD238 JANUARY 2022 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. C No claims to be in conformance with this standard may Ebe made unless all requirements stated in the standard aDre met. E Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, oJr refer to www.jedec.org under Standards and Documents for alter native contact information. Published by ©JEDEC Solid State Technology Association 2022 3103 North 10th Street Suite 240 South Arlington, VA 22201-2108 JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT PLEASE! DON’T VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association C 3103 North 10th Street Suite 240 SouEth Arlington, VA 2D2201-2107 E or refer to www.jedec.org under Standards-Documents/Copyright Information. J Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT C E D E J Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT JEDEC Standard No. 238 HIGH BANDWIDTH MEMORY DRAM (HBM3) Contents 1 Scope ............................................................................................................................................. 1 2 Features ......................................................................................................................................... 1 3 Organization .................................................................................................................................. 2 3.1 Channel Definition ........................................................................................................................ 3 3.1.1 Summary of Per-Channel Signals ................................................................................................. 3 3.1.2 Pseudo Channel ............................................................................................................................. 4 3.1.3 Dual Command Interfaces ............................................................................................................. 5 3.2 Channel Addressing ...................................................................................................................... 6 3.2.1 Bank Groups .................................................................................................................................. 7 3.3 Simplified State Diagram .............................................................................................................. 8 4 Initialization .................................................................................................................................. 9 4.1 HBM3 Power-up and Initialization Sequence ............................................................................... 9 4.2 Controlled Power-off Sequence .................................................................................................. 11 4.3 Initialization Sequence with Stable Power .................................................................................. 12 4.4 Initialization Sequence For Use Of IEEE 1500 Instruction Including Lane Repairs and Channel Disable ......................................................................................................................................... 13 C 5 Mode Registers ............................................................................................................................ 16 6 Operation ..............................................................E....................................................................... 26 6.1 HBM3 Clocking Overview ......................................................................................................... 26 D 6.1.1 WDQS-to-CK Alignment Training ............................................................................................. 28 6.2 HBM3 Data Bus Inversion (DBIac) ........E.................................................................................... 30 6.2.1 Data Bus Inversion (DBIac) ..............J.......................................................................................... 30 6.2.1.1 Internal DBIac State with Read ................................................................................................... 31 6.3 Commands ................................. .................................................................................................. 34 6.3.1 Command Truth Tables ............................................................................................................... 35 6.3.2 Row Commands .......................................................................................................................... 37 6.3.2.1 Row No Operation (RNOP) Command ....................................................................................... 37 6.3.2.2 ACTIVATE (ACT) Command .................................................................................................... 38 6.3.2.3 PRECHARGE (PREpb) and PRECHARGE ALL (PREab) Commands .................................... 41 6.3.2.4 Rounding Rules for Row Access Timings .................................................................................. 45 6.3.2.5 REFRESH Command (REFab) ................................................................................................... 46 6.3.2.6 PER-BANK REFRESH Command (REFpb) .............................................................................. 48 6.3.2.7 Refresh Management (RFM)....................................................................................................... 52 6.3.2.8 Adaptive Refresh Management (ARFM) .................................................................................... 54 6.3.3 Column Commands ..................................................................................................................... 56 6.3.3.1 Column No Operation (CNOP) ................................................................................................... 56 6.3.3.2 Read Command (RD, RDA) ....................................................................................................... 57 6.3.3.3 Write Command (WR, WRA) ..................................................................................................... 67 6.3.3.4 Mode Register Set (MRS) Command ......................................................................................... 75 6.3.4 Power-Mode Commands ............................................................................................................. 77 6.3.4.1 Power-Down (PDE, PDX) .......................................................................................................... 77 6.3.4.2 Self Refresh (SRE, SRX) ............................................................................................................ 83 6.4 Parity ........................................................................................................................................... 87 6.4.1 Command/Address Parity ........................................................................................................... 87 6.4.2 Data Parity ................................................................................................................................... 90 -i- Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT JEDEC Standard No. 238 Contents (cont'd) 6.5 Clock Frequency Change Sequence ............................................................................................ 93 6.6 Temperature Compensated Refresh Reporting ........................................................................... 93 6.6.1 Temperature Compensated Refresh Trip Points.......................................................................... 93 6.6.2 Catastrophic Temperature Sensor ............................................................................................... 93 6.7 Interconnect Redundancy Remapping ......................................................................................... 94 6.7.1 AWORD Remapping .................................................................................................................. 94 6.7.1.1 Row Command Bus – Remapping Table .................................................................................... 94 6.7.1.2 Column Command Bus – Remapping Table ............................................................................... 95 6.7.1.3 AWORD Remapping Examples .................................................................................................. 95 6.7.2 DWORD Remapping .................................................................................................................. 96 6.7.2.1 DWORD Remapping Table ........................................................................................................ 97 6.7.2.2 DWORD Remapping Example ................................................................................................... 98 6.8 HBM3 Loopback Test Modes ................................................................................................... 100 6.8.1 HBM3 Polynomial Structure ..................................................................................................... 101 6.8.1.1 AWORD MISR Polynomial ...................................................................................................... 101 6.8.1.2 DWORD MISR Polynomial ...................................................................................................... 102 6.8.2 General Loopback Modes Features and Behavior..................................................................... 102 6.8.3 AWORD and DWORD Write MISR Modes ............................................................................ 107 6.8.3.1 Test Method for AWORD (Write) MISR Mode .........C.............................................................. 107 6.8.3.2 Test Method for DWORD Write MISR Mode .......................................................................... 108 E 6.8.4 AWORD and DWORD Write Register Modes ......................................................................... 108 D 6.8.4.1 Test Method for AWORD (Write) Register Mode .................................................................... 108 6.8.4.2 Test Method for DWORD Write RegisteEr Mode ...................................................................... 109 6.8.5 DWORD Read Register Mode .................................................................................................. 110 J 6.8.5.1 Test Method for DWORD Read Register Mode ....................................................................... 110 6.8.6 DWORD LFSR Mode (Read dir ection) .................................................................................... 111 6.8.6.1 Test Method for DWORD LFSR Mode (Read direction) ......................................................... 111 6.8.7 AWORD and DWORD Write LFSR Compare Modes ............................................................. 112 6.8.7.1 Test method for AWORD (Write) LFSR Compare Mode ........................................................ 113 6.8.7.2 Test Method for DWORD Write LFSR Compare mode ........................................................... 113 6.9 On-die DRAM ECC .................................................................................................................. 114 6.9.1 ECC Overview .......................................................................................................................... 114 6.9.2 HBM3 On-die ECC Requirements ............................................................................................ 115 6.9.3 DRAM Fault Isolation Requirements........................................................................................ 115 6.9.4 Error Check and Scrub (ECS) ................................................................................................... 115 6.9.5 On-die ECC Transparency Protocol .......................................................................................... 119 6.9.6 ECC Engine Test Mode ............................................................................................................. 120 6.10 WOSC ....................................................................................................................................... 124 6.10.1 WDQS Interval Oscillator ......................................................................................................... 124 6.10.2 tWDQS2DQ_I Offset due to Temperature and Voltage Variation ........................................... 128 6.11 DCA and DCM.......................................................................................................................... 129 6.11.1 Duty Cycle Adjuster (DCA) ...................................................................................................... 129 6.11.2 Duty Cycle Monitor (DCM) ...................................................................................................... 131 6.12 Self Repair ................................................................................................................................. 133 7 Operating Conditions ................................................................................................................ 137 7.1 Absolute Maximum DC Rating ................................................................................................. 137 7.2 Recommended DC Operating Condition .................................................................................. 137 -ii- Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT JEDEC Standard No. 238 Contents (cont'd) 7.3 Operating Temperature ............................................................................................................. 138 8 Electrical Characteristics and DQ/CA Rx ................................................................................. 139 8.1 Leakage Current ........................................................................................................................ 139 8.2 Capacitance ............................................................................................................................... 139 8.3 DQ Rx Voltage and Timing ...................................................................................................... 140 8.4 AWORD Signaling ................................................................................................................... 144 8.5 CK and WDQS Input Signaling ................................................................................................ 144 8.6 Midstack Signaling .................................................................................................................... 146 8.7 Transmit Driver Currents .......................................................................................................... 146 8.8 Output Timing Reference Load ................................................................................................. 146 8.9 Output Voltage Level ................................................................................................................ 147 8.10 Output Rise and Fall Time ........................................................................................................ 147 8.11 Overshoot/Undershoot .............................................................................................................. 148 9 IDD Specification ...................................................................................................................... 149 9.1 IDD and IPP Specification Parameters and Test Conditions .................................................... 149 9.2 IDD and IPP Specifications ....................................................................................................... 158 9.3 IDD6 Specification .................................................................................................................... 158 10 AC Timings ............................................................................................................................... 159 11 Package (Die) Specification ........................................C.............................................................. 166 11.1 Signals ....................................................................................................................................... 166 E 11.2 MicroBump Positions ................................................................................................................ 168 D 11.3 HBM3 Stack Height .................................................................................................................. 169 11.4 HBM3 Bump Map ...................................E.................................................................................. 169 12 HBM DRAM Assembly ............................................................................................................ 200 J 13 Test and Boundary Scan ............................................................................................................ 200 13.1 Direct Access (DA) Test Port .... ................................................................................................ 200 13.1.1 DA Test Port Lockout ............................................................................................................... 201 13.2 IEEE Standard 1500 .................................................................................................................. 201 13.2.1 Interaction Between DA Test Port and IEEE1500 Test Access Port ........................................ 201 13.2.2 IEEE1500 Test Access Port I/O Signals ................................................................................... 202 13.2.3 IEEE1500 Test Access Port Functional Description ................................................................. 202 13.3 Wrapper Data Register (WDR) Types ...................................................................................... 205 13.3.1 Read Only (R) Wrapper Data Registers .................................................................................... 205 13.3.2 Write Only (W) Wrapper Data Registers .................................................................................. 205 13.3.3 Read and Write (R/W) Wrapper Data Registers ....................................................................... 205 13.3.4 WDR Reset State ....................................................................................................................... 205 13.4 IEEE1500 Test Access Port Instruction Encodings .................................................................. 206 13.5 Test Instructions ........................................................................................................................ 207 13.5.1 BYPASS .................................................................................................................................... 209 13.5.2 EXTEST_RX and EXTEST_TX............................................................................................... 210 13.5.3 HBM_RESET............................................................................................................................ 214 13.5.4 MBIST ....................................................................................................................................... 215 13.5.5 SOFT_REPAIR ......................................................................................................................... 216 13.5.6 HARD_REPAIR ....................................................................................................................... 218 13.5.7 DWORD_MISR ........................................................................................................................ 219 13.5.8 AWORD_MISR ........................................................................................................................ 221 13.5.9 CHANNEL_ID.......................................................................................................................... 223 -iii- Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT JEDEC Standard No. 238 Contents (cont'd) 13.5.10 AWORD_MISR_CONFIG ....................................................................................................... 223 13.5.11 DEVICE_ID .............................................................................................................................. 224 13.5.12 TEMPERATURE ...................................................................................................................... 228 13.5.13 MODE_REGISTER_DUMP_SET ........................................................................................... 229 13.5.14 READ_LFSR_COMPARE_STICKY ....................................................................................... 230 13.5.15 SOFT_LANE_REPAIR and HARD_LANE_REPAIR ............................................................ 232 13.5.16 CHANNEL_DISABLE ............................................................................................................. 235 13.5.17 CHANNEL TEMPERATURE .................................................................................................. 236 13.5.18 WOSC_RUN and WOSC_COUNT .......................................................................................... 239 13.5.19 ECS Error Log ........................................................................................................................... 240 13.5.20 HS_REP_CAP ........................................................................................................................... 242 13.5.21 SELF_REP and SELF_REP_RESULTS ................................................................................... 243 13.6 Interaction with Mission Mode Operation ................................................................................ 245 13.7 IEEE1500 Test Port AC Timing Parameters ............................................................................. 246 13.8 Boundary Scan .......................................................................................................................... 252 Tables Table 1 – Single Channel Signal Count ........................................C...................................................................... 3 Table 2 – Global Signal Count ............................................................................................................................ 3 E Table 3 – Array Access Timings Counted Individually Per Pseudo Channel ................................................... 4 D Table 4 – HBM3 Channel Addressing ................................................................................................................ 6 Table 5 – Bank Group Assignments ..........................E.......................................................................................... 7 Table 6 – Command Sequence Affected by Bank Groups ................................................................................. 7 J Table 7 – Initialization Timing Parameters ....................................................................................................... 10 Table 8 – Power Ramp Conditions .............. ...................................................................................................... 10 Table 9 – Power Supply Conditions .................................................................................................................. 11 Table 10 – HBM3 Mode Register Overview .................................................................................................... 17 Table 11 – Mode Register 0 (MR0) .................................................................................................................. 18 Table 12 – Mode Register 1 (MR1) .................................................................................................................. 18 Table 13 – Mode Register 2 (MR2) .................................................................................................................. 19 Table 14 – Mode Register 3 (MR3) .................................................................................................................. 19 Table 15 – Mode Register 4 (MR4) .................................................................................................................. 19 Table 16 – Mode Register 5 (MR5) .................................................................................................................. 20 Table 17 – Mode Register 6 (MR6) .................................................................................................................. 20 Table 18 – Mode Register 7 (MR7) .................................................................................................................. 21 Table 19 – DWORD MISR Read and Write Operations in Loopback Test Mode (MR7 OP0=1) ................. 22 Table 20 – Mode Register 8 (MR8) .................................................................................................................. 22 Table 21 – Mode Register 9 (MR9) .................................................................................................................. 23 Table 22 – Mode Register 10 (MR10) .............................................................................................................. 23 Table 23 – Mode Register 11 (MR11) .............................................................................................................. 24 Table 24 – Mode Register 12 (MR12) .............................................................................................................. 24 Table 25 – Mode Register 13 (MR13) .............................................................................................................. 24 Table 26 – Mode Register 14 (MR14) .............................................................................................................. 25 Table 27 – Mode Register 15 (MR15) .............................................................................................................. 25 Table 28 – Phase Detector and DERR Signal Behavior ................................................................................... 28 Table 29 – DBI(ac) Truth Table ........................................................................................................................ 31 -iv- Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT JEDEC Standard No. 238 Contents (cont'd) Table 30 – Row Commands Truth Table .......................................................................................................... 35 Table 31 – Column Commands Truth Table ..................................................................................................... 36 Table 32 – Options for issuing PREab and PREpb commands ........................................................................ 37 Table 33 – Precharge and Auto Precharge Timings ......................................................................................... 44 Table 34 – Refresh Counter Increments (Example for HBM3 Configurations with 16 Banks) ..................... 50 Table 35 – Refresh and Per-Bank Refresh Command Scheduling Requirements ........................................... 51 Table 36 – Mode Register Definition for Adaptive RFM Levels ..................................................................... 54 Table 37 – RFM Commands Perceived by HBM3 DRAM ............................................................................. 55 Table 38 – Signal Groups for Read Data De-Skew .......................................................................................... 66 Table 39 – Signal Groups for Write Data De-Skew ......................................................................................... 74 Table 40 – Pin State Description in Power Down............................................................................................. 80 Table 41 – Pin State Description in Self Refresh .............................................................................................. 86 Table 42 – Command/Address Parity Function Table ...................................................................................... 87 Table 43 – Data Parity Function Table.............................................................................................................. 91 Table 44 – Temperature Compensated Refresh Trip Points ............................................................................. 93 Table 45 – AWORD - Row Command Bus Remapping .................................................................................. 94 Table 46 – AWORD - Column Command Bus Remapping ............................................................................ 95 Table 47 – Original Lane Assignment - Channel a - AWORD Column Repair .............................................. 95 Table 48 – Remapped Lane Assignment - Channel a - AWORD CColumn Repair .......................................... 95 Table 49 – Original Lane Assignment - Channel a - AWORD Row Repair ................................................... 96 E Table 50 – Remapped Lane Assignment - Channel a - AWORD Row Repair ............................................... 96 D Table 51 – DWORD Remapping (1 Byte) ........................................................................................................ 97 Table 52 – Original DWORD Lane Assignment - ChEannel a – Byte [1:0] ..................................................... 98 Table 53 – Remapped DWORD Lane Assignment - Channel a – Byte [1:0] .................................................. 98 J Table 54 – MISR Function Table .................................................................................................................... 101 Table 55 – ECS Modes ................................ .................................................................................................... 116 Table 56 – t per Stack (ECS independent of SID) ................................................................................... 117 ECSint Table 57 – Error Overwrite Priority Rules to Handle Multiple Error Logging ............................................. 118 Table 58 – Transparency Attributes and Their Access/Control Mechanism ................................................. 119 Table 59 – Severity Encodings on the SEV pins ............................................................................................ 119 Table 60 – Severity Transmission on READ .................................................................................................. 119 Table 61 – ECC Engine Test Modes ............................................................................................................... 120 Table 62 – Example of Error Vectors and Corresponding Severity ............................................................... 122 Table 63 – WDQS Oscillator Matching Error Specification .......................................................................... 128 Table 64 – DCA Maximum Offset and Step Size ........................................................................................... 129 Table 65 – DCM Measurement Result ............................................................................................................ 131 Table 66 – SELF_REP Instruction vs Stack Height ....................................................................................... 133 Table 67 – SELF_REPAIR Timings ............................................................................................................... 134 Table 68 – SELF_REP – Expected DRAM Behavior When Resources Shared ........................................... 135 Table 69 – Absolute Maximum DC Ratings ................................................................................................... 137 Table 70 – Recommended DC Operating Condition ...................................................................................... 137 Table 71 – Operating Temperature .................................................................................................................. 138 Table 72 – Input Leakage Current ................................................................................................................... 139 Table 73 – Input/Output Capacitance .............................................................................................................. 139 Table 74 – Input Receiver Voltage Level Specification ................................................................................. 141 Table 75 – AWORD Receiver Voltage Level Specification .......................................................................... 144 Table 76 – CK and WDQS Input Voltage Level Specification ...................................................................... 144 -v- Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT JEDEC Standard No. 238 Contents (cont'd) Table 77 – Differential Input Level for WDQS_t, WDQS_c ......................................................................... 145 Table 78 – Differential Input Slew Rate Definition for WDQS_t, WDQS_c ................................................ 145 Table 79 – Midstack Parameter Specification ................................................................................................. 146 Table 80 – Transmit Driver Current Specification ......................................................................................... 146 Table 81 – Output Voltage Level .................................................................................................................... 147 Table 82 – Overshoot/Undershoot Specification for AWORD and DWORD Signals ................................. 148 Table 83 – Basic IDD/IDDQ/IPP/IDDQL Measurement Conditions ............................................................ 150 Table 84 – Example of Timings used for IDD Measurement-Loop Pattern .................................................. 152 Table 85 – IDD0 Measurement-Loop Pattern ................................................................................................. 153 Table 86 – IDD4R Measurement-Loop Pattern .............................................................................................. 154 Table 87 – IDD4W Measurement-Loop Pattern ............................................................................................. 155 Table 88 – IDD5P Measurement-Loop Pattern .............................................................................................. 156 Table 89 – IDD7 Measurement-Loop Pattern ................................................................................................. 157 Table 90 – IDD and IPP Specification Example ............................................................................................. 158 Table 91 – IDD6 Specification ........................................................................................................................ 158 Table 92 – Timings Parameters (Part 1) .......................................................................................................... 159 Table 93 – Timings Parameters (Part 2) .......................................................................................................... 161 Table 94 – I/O Signal Description ................................................................................................................... 166 Table 95 – Geometric Parameters of the Staggered MicroBump PCattern ...................................................... 168 Table 96 – HBM3 Stack Height ...................................................................................................................... 169 E Table 97 – Legend............................................................................................................................................ 169 D Table 98 – HBM3 Bump Map Footprint – Geographical Overview (not to scale) ....................................... 170 Table 99 – HBM3 Bump Map Footprint : Columns E1 to 36 .......................................................................... 171 Table 100 – HBM3 Bump Map Footprint : Columns 37 to 74 ...................................................................... 176 J Table 101 – HBM3 Bump Map Footprint : Columns 75 to 90 ...................................................................... 181 Table 102 – HBM3 Bump Map Footprint : Columns 91 to 118 .................................................................... 186 Table 103 – HBM3 Bump Map Footprint : Columns 119 to 148 .................................................................. 193 Table 104 – Direct Access (DA) Pin Allocation ............................................................................................. 200 Table 105 – Test Access Port Signal Status .................................................................................................... 202 Table 106 – IEEE1500 Test Port Signal List and Description ....................................................................... 202 Table 107 – WIR Channel Selection Definition ............................................................................................. 206 Table 108 – Instruction Register Encodings ................................................................................................... 207 Table 109 – BYPASS Wrapper Data Register ................................................................................................ 209 Table 110 – Wrapper Boundary Register (WBR) ........................................................................................... 211 Table 111 – HBM_RESET Wrapper Data Register ....................................................................................... 214 Table 112 – RESET_n and HBM_RESET Truth Table ................................................................................. 215 Table 113 – MBIST Wrapper Data Register ................................................................................................... 215 Table 114 – SOFT_REPAIR Wrapper Data Register` ................................................................................... 217 Table 115 – HARD_REPAIR Wrapper Data Register ................................................................................... 218 Table 116 – DWORD_MISR Wrapper Data Register.................................................................................... 219 Table 117 – AWORD_MISR Wrapper Data Register.................................................................................... 222 Table 118 – CHANNEL_ID Wrapper Data Register ..................................................................................... 223 Table 119 – AWORD_MISR_CONFIG Wrapper Data Register .................................................................. 224 Table 120 – DEVICE_ID Wrapper Data Register .......................................................................................... 225 Table 121 – TEMPERATURE Wrapper Data Register ................................................................................. 228 Table 122 – MODE_REGISTER_DUMP_SET Wrapper Data Register ...................................................... 229 Table 123 – READ_LFSR_COMPARE_STICKY Wrapper Data Register ................................................. 231 -vi- Downloaded by 65 56 (cdm_lj@163.com) on Jun 13, 2022, 1:12 am PDT

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