Hardware-Software Co-Design, Acceleration and Prototyping of Control Algorithms on ...

138 Pages·2016·5.2 MB·English

by  Desta Kumsa Edosa

UNLV Theses, Dissertations, Professional Papers, and Capstones
12-1-2012
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Desta Kumsa Edosa
University of Nevada, Las Vegas
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Edosa, Desta Kumsa, "Hardware-Software Co-Design, Acceleration and Prototyping of Control Algorithms
on Reconfigurable Platforms" (2012). UNLV Theses, Dissertations, Professional Papers, and Capstones.
1728.
http://dx.doi.org/10.34917/4332709
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HARDWARE-SOFTWARE CO-DESIGN, ACCELERATION AND PROTOTYPING
OF CONTROL ALGORITHMS ON RECONFIGURABLE PLATFORMS

By

Desta Kumsa Edosa
Bachelor of Science in Electrical Engineering
Bahir Dar University, Ethiopia
June 2007
A thesis submitted in partial fulfillment of
the requirements for the

Master of Science in Electrical Engineering

Department of Electrical and Computer Engineering
Howard R. Hughes College of Engineering
The Graduate College

University of Nevada, Las Vegas
December 2012
THE GRADUATE COLLEGE

We recommend the thesis prepared under our supervision by

Desta Kumsa Edosa

entitled

Hardware-Software Co-Design, Acceleration and Prototyping of Control Algorithms on
Reconfigurable Platforms

be accepted in partial fulfillment of the requirements for the degree of

Master of Science in Electrical Engineering
Department of Electrical and Computer Engineering

Venkatesan Muhtukumar, Ph.D., Committee Chair

Emma Regentova, Ph.D., Committee Member

Sahjendra Singh, Ph.D., Committee Member

Ajoy K. Datta, Ph.D., Graduate College Representative

Tom Piechota, Ph.D., Interim Vice President for Research &
Dean of the Graduate College

December 2012

ii
ABSTRACT
HARDWARE-SOFTWARE CO-DESIGN, ACCELERATION AND
PROTOTYPING OF CONTROL ALGORITHMS ON RECONFIGURABLE
PLATFORMS
by
Desta Kumsa Edosa
Dr. Venkatesan Muthukumar, Examination Committee Chair
Associate Professor, Electrical and Computer Engineering,
University of Nevada, Las Vegas
Differential equations play a significant role in many disciplines of science and
engineering. Solving and implementing Ordinary Differential Equations (ODEs) and
partial Differential Equations (PDEs) effectively are very essential as most complex
dynamic systems are modeled based on these equations. High Performance Computing
(HPC) methodologies are required to compute and implement complex and data intensive
applications modeled by differential equations at higher speed. There are, however, some
challenges and limitations in implementing dynamic system, modeled by non-linear
ordinary differential equations, on digital hardware. Modeling an integrator involves data
approximation which results in accuracy error if data values are not considered properly.
Accuracy and precision are dependent on the data types defined for each block of a
system and subsystems. Also, digital hardware mostly works on fixed point data which
leads to some data approximations. Using Field Programmable Gate Array (FPGA), it is
possible to solve ordinary differential equations (ODE) at high speed. FPGA also
provides scalable, flexible and reconfigurable features.
The goal of this thesis is to explore and compare implementation of control
algorithms on reconfigurable logic. This thesis focuses on implementing control
algorithms modeled by second and fourth order PDEs and ODEs using Xilinx System
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Generator (XSG) and LabVIEW FPGA module synthesis tools. Xilinx System Generator
for DSP allows integration of legacy HDL code, embedded IP cores, MATLAB
functions, and hardware components targeted for Xilinx FPGAs to create complete
system models that can be simulated and synthesized within the Simulink environment.
The National Instruments (NI) LabVIEW FPGA Module extends LabVIEW graphical
development to Field-Programmable Gate Arrays (FPGAs) on NI Reconfigurable I/O
hardware. This thesis also focuses on efficient implementation and performance
comparison of these implementations. Optimization of area, latency and power has also
been explored during implementation and comparison results are discussed.

iv
ACKNOWLEDGMENTS
I would like to express my sincere and deepest heartily gratitude to my professor Dr.
Venkatesan Muthukumar whose remarkable mentorship and guidance has been with me
from the start to the end of this work. A plain "thank you" phrase is really too simple to
express his indispensable guidance throughout this thesis work. He has taught me
learning by being challenged and finding different approaches to solve problems. I am
really appreciative for his constant follow-ups and his valuable time.
I am also very thankful to my advisory committees and my professors, Drs. Sahjendar
Singh and Emma Regentova, who without reserve have helped me with material
resources and in explaining many concepts for this thesis. My special thanks also go to
Dr. Ajoy Datta for being my Graduate College Representative.
My dearest wife, Lattuu, deserves special thanks first for loving me and determined to
be my wife forever and second for being an excellent young mom by taking great
responsibility in caring for our twin sons when situations have been challenging to her;
tolerating the pain of loneliness but yet encouraged me to go forward in my education.
I am very thankful to my parents, Obbo Kumsaa Iddoosaa and Aadde Baqqalee
Gaja'aa, for without their persistent commitment and sacrifice my being here could have
been unimaginable. They showed me their unbiased love, taught me what perseverance
mean, gave me the chance that they themselves never had in their entire life. Now, I can
see the world broadly through the door they opened for me. Thank you, Mom and Dad!
Lastly, but not least, I am grateful to all my brothers, sisters, relatives and friends
who stood beside me with their moral support until the end of this thesis.

GALATA
Warra koo, Obbo Kumsaa Iddoosaa fi Aadde Baqqalee Gaja'aa, carraa barumsaa osoo
hin argatiin, abdii ifaa tokko fulduratti ilaaluun, anatti dhubbanii, tabba jireenyaa bu'anii
bahanii, bifa lama natti baasanii, natti daaranii,asiin nagaahaniif; Haadha manaa koo,
Lattuu, dhibee yaaddoo fi kophummaa obsaan dandeessee, daa’ima keenya lamaan faana
qophaa waliin rakkachaa, itti cinniinnattee guddisaarra haamilee isheen na duukee buute
jaabadhu naan jetteef; obbolaa/tii wan koo warra fakkeenyaa na fudhachuun isaanii itti
gaafatamummaa guddaa natti ta’ee akkan cimu na godheef; akkasumas hiriyyoota koo fi
firoottan koo warra haamilee fi gorsa isaaniin na duukaa turan maraaf galatni koo guddaa
dha.

v
DEDICATION

This work is dedicated to
My sons
Obsineet and Obsinuun

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ABSTRACT……………………………………………………………………... iii
ACKNOWLEDGMENTS………………………………………………………... v
GALATA………………………………………………………………………… .v
DEDICATION…………………………………………………………………… vi
LIST OF TABLES……………………………………………………………... xiii
LIST OF FIGURES…………………………………………………………….. xiv
CHAPTER 1 INTRODUCTION…………………………………………………. 1
1.1 The need for High Performance Computing…………………………….. 1
1.2 Research Objectives……………………………………………………... 5
CHAPTER 2 BACKGROUND…………………………………………………... 9
2.1 Trends in High Performance Computing………………………………... 9
2.2 LabVIEW………………………………………………………………. 12
2.3 LabVIEW FPGA Module……………………………………………….14
2.4 LabVIEW Real-Time Module…………………………………………..16
2.5 LabVIEW Control Design and Simulation Module……………………. 17
2.6 MATLAB /Simulink…………………………………………………… 18
CHAPTER 3 METHODOLOGY……………………………………………….. 20
3.1. Software Simulation……………………………………………………. 22
3.2. Hardware-Software Co-Simulation…………………………………….. 23
3.2.1. HW-SW Co-Simulation in XSG……………………………………. 23
3.2.2. LabVIEW Real-Time HW/SW Co-Simulation……………………... 25
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3.2.3. LabVIEW FPGA Hardware Software Co-Simulation……………… 26
3.3. Hardware Implementation Emulation………………………………….. 27
3.4. Hardware-in-the-Loop (HIL) Simulation………………………………. 27
3.5. Hardware-in-the-Loop (HIL) Emulation………………………………..29
CHAPTER 4 APPLICATION………………………………………………….. 30
4.1. Inferior Olive Neuron………………………………………………….. 30
4.2. Mathematical Model for Inferior Olive Neuron………………………...31
4.3. Inferior Olive Neuron Synchronization…………………………………32
4.3.1. Synchronization of IONs Using Gain Feedback Controller…………33
4.3.2. Synchronization Using Filter Feedback Controller…………………. 35
4.4. ION Driven PID Controlled DC Motor…………………………………36
4.4.1. DC Motor…………………………………………………………… 36
4.4.2. PID Controller………………………………………………………. 39
4.5. Lorenz Chaos System…………………………………………………….. 40
4.5.1. Control of Lorenz Chaos System………………………………………. 41
CHAPTER 5 IMPLEMENTATION……………………………………………. 42
5.1. Introduction to FPGA…………………………………………………... 42
5.2. Hardware Platforms……………………………………………………. 44
5.2.1. Spartan-3A DSP 3400A…………………………………………….. 45
5.2.2. NI PXI-8106 Embedded Controller………………………………… 45
5.3. Software Platforms……………………………………………………... 47
viii
5.3.1. Xilinx System Generator (XSG)……………………………………. 47
5.3.2. LabVIEW FPGA Module……………………………………………49
5.4. Implementation Process………………………………………………... 49
5.5. Implementation of Single Inferior Olive Neuron (ION)……………….. 51
5.5.1. Single ION Simulation Model……………………………………….51
5.5.1.1. MATLAB /Simulink Model ......................................................... 51
5.5.1.2. LabVIEW Model .......................................................................... 52
5.5.1.3. LabVIEW Real-Time Model ........................................................ 54
5.5.2. ION HW-SW Co-Simulation……………………………………….. 55
5.5.2.1. MATLAB XSG HW-SW Co-Simulation .................................... 55
5.5.2.2. LabVIEW FPGA HW-SW Co-Simulation .................................. 57
5.5.2.3. Development Flow in LabVIEW FPGA ...................................... 59
5.5.3. Hardware-in-Loop (HIL) Simulation………………………………. 62
5.5.3.1. Implementation of PID Controller ............................................... 63
5.5.3.2. Implementations of DC Motor ..................................................... 63
5.5.4. Hardware-in-the-Loop (HIL) Emulation…………………………… 70
5.5.4.1. HIL Emulation Implementation in LabVIEW FPGA .................. 71
5.5.4.2. HIL Emulation Implementation in XSG ...................................... 72
5.5.5. Hardware Emulation…………………………………………………74
5.6. Implementation of Synchronizations of IONs…………………………. 74
5.6.1. Implementation Synchronizations of Two IONs Using Gain Controller
………………………………………………………………………. 74
5.6.1.1. Simulation .................................................................................... 74
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