Graphs in VLSI

356 Pages·2022·17.524 MB·English

by  Rassul Bairamkulov, Eby G. Friedman

Rassul Bairamkulov
Eby G. Friedman
Graphs in VLSI
Graphs in VLSI
Rassul Bairamkulov • Eby G. Friedman
Graphs in VLSI
RassulBairamkulov EbyG.Friedman
UniversityofRochester UniversityofRochester
Rochester,NY,USA Rochester,NY,USA
ISBN978-3-031-11046-7 ISBN978-3-031-11047-4 (eBook)
https://doi.org/10.1007/978-3-031-11047-4
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Preface
Advancesinsemiconductorfabricationtechnologyhaveproducedexplosivegrowth
inthenumberoftransistorswithinanintegratedcircuit(IC).Moderndevicesconsist
of dozens of components, thousands of modules, millions of registers, and many
billions of transistors. Despite the capacity to fabricate exorbitant quantities of
nanoscaledevices,convertingthesetransistorsintofunctionalproductsisacomplex
multifacetedchallenge.Synchronization,powerintegrity,logicsynthesis,andphys-
ical layout represent only a small portion of the many issues encountered during
the very large scale integration (VLSI) design and analysis process. These issues
are only expected to grow in complexity as microelectronic systems evolve due
to three-dimensional integration, shrinking transistor dimensions, and emerging,
beyondCMOStechnologies.
Sinceeveryintegratedsystemisfundamentallyanetwork,solutionstomanyof
the challenges inherent to VLSI can be resolved using graph theory. Many forms
of graphs naturally occur at each level of the VLSI system design hierarchy. At
the architectural level, register allocation is often viewed from a graph coloring
perspective. Synchronization of the sequential logic is achieved by optimizing
timinggraphs.TheelectricalcharacteristicsofaVLSIsystemaredeterminedfrom
the analysis of circuit graphs. Graph-based partitioning, floorplanning, placement,
androutingareintegralpartsofthemulti-tieredVLSIphysicallayoutprocess.
ThequalityandcomplexityofICshavebeengreatlyenhancedbygraphtheoretic
techniques and algorithms. In return, novel practical VLSI applications have
revitalizedcertainsubfieldsofgraphtheory.Classicgraphtheoreticproblems,such
asSteinerminimaltrees,pathfinding,andgraphpartitioning,havebeenextensively
studied and applied, in no small part, due to the practical effectiveness of graph
theorytothedesignandanalysisofVLSIsystems.Avirtuouscycleoftheoryand
application has greatly advanced both graph theory and ever more powerful VLSI
systems.
This book is based on the body of research produced by Rassul Bairamkulov
duringhisdoctoralstudiesfrom2017to2022attheUniversityofRochesterunder
thesupervisionofProfessorEbyG.Friedman.Twoobservationsinspiredthisbook:
vii
viii Preface
(cid:129) Despite the significance of graph theory to the design of VLSI circuits and
systems, a comprehensive review of applications of graph theory in VLSI is
currentlymissingfromtheliterature.BooksdiscussingtheoverallVLSIdesign
process typically only provide a basic description of graph theory, while books
focusing on graph theory contain few applications relating to the VLSI design
process.BooksdiscussingspecializedtopicsinVLSIalsoexist,yetthesebooks
onlycoverasmallsubsetofgraphtheoreticapplications.
(cid:129) DespitetheapparentomnipresenceofgraphsintheVLSIsystemdesignprocess,
the authors believe that the full potential of graph theory has yet to be fully
realizedinmodernVLSIdesigntools.ManyareasoftheVLSIdesignprocess,
such as system exploration and the integration of emerging technologies, will
requirenoveldesignmethodologiesandalgorithms,manyofwhichrelyongraph
theory.
These observations are reflected in the organization of this book. The first half
of the book is focused on existing applications of graph theory and algorithms
to the design of integrated systems. After a brief description of the fundamental
concepts of graph theory, common applications of graph theory at different levels
of abstraction within the VLSI system design process are discussed. Individual
chapters are dedicated to synchronization and circuit analysis, two particularly
important issues in the VLSI design process which are deeply affected by graph
theory.
The second half of the book is focused on three novel unorthodox applications
of graph theory. The first application is the Infinity Mirror Technique (IMT) – a
constanttimemeshanalysisalgorithmacceleratingtheIRdropanalysisprocessin
practical on-chip power networks by several orders of magnitude. An IMT-based
computationally efficient algorithm for on-chip voltage regulator distribution is
alsodescribed.Thesecondapplicationisrelatedtotheexplorationofsystem-level
power delivery. The SPROUT – Smart Power ROUTing algorithm is presented to
efficiently produce a prototype of a board-level power network, enabling efficient
analysiswithhigh-levelarchitecturaltradeoffs,suchasthenumberoflayerswithin
the board or the position of discrete components. The second half of the book is
completed with QuCTS – single flux Quantum Clock Tree Synthesis algorithm,
which describes a graph-based algorithm to satisfy the stringent requirements for
clockdistributionnetworksinsuperconductiveelectronics.
Due to the focus on the VLSI design process, this book is expected to become
a useful addition to the library of engineers, researchers, and students working in
theareasofVLSIsystemdesignandcomputerscience.Forprofessionalsworking
in the design of VLSI systems (typically electrical and computer engineers and
computerscientists),thisbookprovidesadeeperinsightintothetheorybehindmany
establisheddesigntechniquesbasedongraphtheory,suchasclockskewscheduling,
systempartitioning,circuitanalysisandoptimization,andinterconnectrouting.For
mathematiciansandcomputerscientists,thebookelucidatesthelinkbetweengraph
theoryandthedesignandanalysisofVLSIcircuitsandsystems.
Acknowledgments
Theauthorswouldliketoacknowledgethesupportofourmanycollaboratorswho
facilitated the development of this book. The authors would like to thank Charles
B. Glaser and Shabib Shaikh from Springer for their assistance in the publishing
process. The authors are very grateful to Dr. Mikhail Popovich from Google, Dr.
Kan Xu and Dr. Juan S. Ochoa from Apple, Dr. Abinash Roy from Intel, Mr.
Mahalignam Nagarajan and Dr. Vaishnav Srinivas from Qualcomm Technologies,
andMr.JamilKawafromSynopsys,fortheircontinuedsupportandcollaboration
duringtheresearchprojectsthatconstituteaconsiderablepartofthisbook.Special
thanks are reserved for Tahereh Jabbari from the High Performance Integrated
Circuit Design and Analysis Laboratory for sharing her expertise in single flux
quantumcircuitdesign.
This research is supported in part by the National Science Foundation under
Grant Nos. CCF-1329374, CCF-1526466, CCF-1716091, Intelligence Advanced
Research Projects Activity under Grant Nos. W911NF-14-C-0089 and W911NF-
17-9-0001,AmericanInstituteforManufacturingIntegratedPhotonicsunderAward
No. 059447-007, the Intel Collaborative Research Institute for Computational
Intelligence, Singapore Ministry of Education Tier 2 under Grant No. MOE2014-
T2-2-105,andgrantsfromCiscoSystems,Google,OeC,Qualcomm,andSynopsys.
Rochester,NY,USA RassulBairamkulov
Rochester,NY,USA EbyG.Friedman
ix
Contents
1 Introduction................................................................. 1
1.1 PrecursorsofVLSI................................................... 3
1.2 TheriseofVLSI...................................................... 6
1.3 Outlineofbook....................................................... 10
2 Graphfundamentals ....................................................... 13
2.1 Graphcategories...................................................... 15
2.1.1 Hypergraph ................................................. 16
2.1.2 Graphswithparalleledges................................. 17
2.1.3 Graphswithoutparalleledges.............................. 18
2.1.4 Weightedgraph............................................. 19
2.1.5 Directedgraph.............................................. 21
2.2 Inter-graphrelationships............................................. 21
2.3 Graphexploration.................................................... 23
2.4 Bipartitegraph........................................................ 25
2.5 Directedacyclicgraph ............................................... 25
2.6 Tree ................................................................... 27
2.7 Commonproblemsingraphtheory ................................. 29
2.7.1 Pathfinding.................................................. 31
2.7.2 Spanningtree ............................................... 40
2.7.3 Graphcoloring.............................................. 49
2.7.4 Topologicalsorting......................................... 52
2.8 Summary.............................................................. 55
3 GraphsinVLSIcircuitsandsystems..................................... 59
3.1 GraphsasaVLSIabstractiontool................................... 60
3.2 Registertransferlevel................................................ 63
3.2.1 Registerallocation.......................................... 64
3.2.2 Taskscheduling............................................. 68
3.2.3 Synchronization............................................. 72
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xii Contents
3.3 Gatelayer............................................................. 74
3.3.1 Orderedbinarydecisiondiagram.......................... 76
3.3.2 And-invertergraph.......................................... 79
3.4 Circuitlayer .......................................................... 81
3.4.1 Laplacianmatrixofacircuitgraph........................ 82
3.5 Physicallayer......................................................... 87
3.5.1 Partitioning.................................................. 88
3.5.2 Floorplanning............................................... 91
3.5.3 Placement................................................... 92
3.5.4 Routing...................................................... 95
3.6 Summary.............................................................. 97
4 SynchronizationinVLSI .................................................. 101
4.1 Graph-basedtiminganalysis......................................... 105
4.1.1 Timingconstraintsinsynchronoussystems............... 106
4.2 Clockskewscheduling............................................... 117
4.2.1 Robustness.................................................. 117
4.2.2 Performance................................................. 123
4.2.3 Power........................................................ 126
4.3 Clocktreesynthesis.................................................. 131
4.3.1 Clocktreetopology......................................... 132
4.3.2 Clocktreeembedding ...................................... 141
4.3.3 Methodofmeansandmedians............................. 141
4.3.4 Deferredmergeembedding ................................ 143
4.3.5 Elmoredelay................................................ 144
4.3.6 Boundedskewtree.......................................... 144
4.3.7 Usefulskewtree............................................ 145
4.4 Summary.............................................................. 146
5 Circuitanalysis ............................................................. 149
5.1 Modifiednodalanalysis.............................................. 151
5.2 Iterativenumericalmethods ......................................... 155
5.2.1 Domaindecomposition..................................... 158
5.2.2 H-matrix.................................................... 161
5.2.3 Multigridmethods.......................................... 164
5.3 Non-MNAtechniques................................................ 167
5.3.1 Scatteringparameters....................................... 167
5.3.2 Randomwalks.............................................. 169
5.3.3 Latticegraph................................................ 172
5.4 Summary.............................................................. 176
6 Effectiveresistanceoftruncatedinfinitemeshstructures.............. 177
6.1 Historicalperspective ................................................ 178
6.2 Electricpotentialinaninfinitemesh................................ 179
6.3 Electricpotentialwithinatruncatedinfinitemesh.................. 182
6.3.1 Modelingtruncationwithimage........................... 182
6.3.2 Integralexpressionsforeffectiveresistance............... 185