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Glonass/GPS de-rotation and filtering with ADC sampling at 60-80 MSPS PDF

32 Pages·2014·2.27 MB·English
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Preview Glonass/GPS de-rotation and filtering with ADC sampling at 60-80 MSPS

US008604974B2 United States Patent (12) (10) Patent N0.: US 8,604,974 B2 Ganeshan et al. (45) Date of Patent: Dec. 10, 2013 (54) GLONASS/GPS DE-ROTATION AND (58) Field of Classi?cation Search FILTERING WITH ADC SAMPLING AT 60-80 USPC ............. .. 342/357.4, 357.46, 357.73, 357.77; MSPS 375/340, 350, 355 See application ?le for complete search history. (71) Applicant: Texas Instruments Incorporated, Dallas’ TX (Us) (56) References Cited (72) Inventors: Saravana Kumar Ganeshan, Kamataka U'S' PATENT DOCUMENTS (IN); Bijoy Bhukanias Kamamka (IN); 7,346,134 B2 * 3/2008 Smith ,,,,,,,,,,,,,,,,,,,,,,,,, ,, 375/346 Allalld K311112111, Karnataka (1N) 2009/0068974 A1 * 3/2009 Smith . 455/304 (73) Assignee: Texas Instruments Incorporated, * Cited by examiner Dallas’ TX (Us) Primary Examiner * Dao Phan ( * ) Notice: Subject to any disclaimer, the term of this (74) A210" "6)’; Age”?! 0" F17’ m * Lawrence J- Bassuk; Wade patent is extended or adjusted under 35 J~ Brady’ HI; Fredenck J~Te1eCky> J1 U.S.C. 154(b) by 0 days. (57) ABSTRACT (21) APP1~ NOJ 13/850,802 An electronic circuit separates frequency-overlapped GLO _ NASS and GPS overlapped in an approximately 4 MHZ pass (22) Flled: Mar‘ 26’ 2013 band. The circuit uses a multiple-path analog-to-digital con _ _ _ verter circuit (ADC). A sampling rate circuit is coupled to (65) Pnor Pubhcatlon Data concurrently operate the analog-to-digital converter circuit at US 2013/0229306 A1 Sep 5, 2013 a sampling rate between about 60 Msps and about 80 Msps. A _ _ digital processing circuit includes storage de?ning complex Related U's' Apphcatlon Data de-rotation and loW pass ?ltering. The digital processing cir (62) Division of application No, 12/897,039, ?led on Oct, cuit is fed by the analog-to-digital converter circuit and is 4, 2010, now Pat, No, 8,427 ,366, operable A) to establish an access rate and respective distinct phase increments for the complex de-rotation, B) to execute (30) Foreign Application Priority Data the complex de-rotation by combinations of trigonometric multiplications using the distinct phase increments approxi Jul. 27, 2010 (IN) ......................... .. 2l3l/CHE/20l0 mately concurrently and C) to execute the low pass ?ltering on the complex de-rotation resulting at the access rate and (51) Int- Cl- respective distinct phase increments, thus delivering GPS and Gols 19/33 (2010-01) Glonass signals separated from each other. (52) US. Cl. USPC ................................................... .. 342/357.73 19 Claims, 14 Drawing Sheets 222,224 I 40 410 GLONASS DIGITAL \ \ = FILTER CHAIN —> ANALOG IQ COMMON PART IQ (H9 7A) TO DIGITAL ' / > OF DIGITAL ’ / CONVERTER (FIG. 5) GPS D|G|TA|_ I > FILTER CHAIN —> F (FIG. 7B) 1 45 / SAMP US. Patent Dec. 10, 2013 Sheet 4 0f 14 US 8,604,974 B2 | | l | VIN : , , , , 1-BITFLASH : I STAGE1 21> STAGE2 :> FLASH3 I I : | | : AMP SHARED | L {5 i J)T 4/? CS1 —o\<> FLASH 2 0/6 I VOUT FLASH 3 CASCADE FIG. 3B US. Patent Dec. 10, 2013 Sheet 5 0f 14 US 8,604,974 B2 .1 FsAlvlP MSB 320.2 VCM 310.2\ " 32 .3 VCM 310.N/ FIG. 3C 2FsAlvlP + | ADC FIG. 3D US. Patent Dec. 10, 2013 Sheet 6 0f 14 US 8,604,974 B2 222,224 140 410 GLONASS DIGITAL \ \ FILTER CHAIN _> ANALOG IQ COMMON PART IQ (FIG-TA) TO DIGITAL ' /> OF DIGITAL ’ CONVERTER (FIG. 5) GPS D|G|TA|_ T FILTER CHAIN _> F (FIG. 7B) 145/ SAMP FIG. 4 430 410 \ / T0 DC DC OFFSET CORRECTION<— HW ENGINE <_ DACs (F|G.1) “sPuR AGC HW PROGRAMMABLE T v A O 22;; ENGINE ‘H REAL NOTCH = BLANK FREEZE F'LTER JAMMER SPUR J’ IQMC $4 CALIBRATION L4 55O\> t A AOOIANOQ 1.4, f ‘ IQMC 1.7, >GLOT£ASS CHANNEL ’ ' COMPENSATION ’ ' GPS FIG. 5 US. Patent Dec. 10, 2013 Sheet 7 0f 14 US 8,604,974 B2

Description:
NASS and GPS overlapped in an approximately 4 MHZ pass. (22) Flled: Mar' 26' .. sampling rate Fsamp for LPADC 1401 and 140Q. 1n the receiver
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