Function/Architecture Optimization and Co-Design of Embedded Systems

254 Pages·2000·8.415 MB·English

by  Bassam Tabbara, Abdallah Tabbara, Alberto Sangiovanni-Vincentelli (auth.)

FUNCTIONI ARCHITECTURE
OPTIMIZATION AND
CO-DESIGN OF EMBEDDED
SYSTEMS
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
FUNCTION/ ARCHITECTURE
OPTIMIZATION AND
CO-DESIGN OF EMBEDDED
SYSTEMS
Bassam TABBARA
Novas Software, Ine.
San Jose, California, USA
•
Abdallah TABBARA
University of California at Berkeley
Berkeley, California, USA
•
Alberto SANGIOVANNI-VINCENTELLI
University of California Berkeley
Berkeley, California, USA
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication Data
Tabbara, Bassam, 1971-
Functionlarchitecture optimization and co-design of embedded systems /
Bassam Tabbara, Abdallah Tabbara, Alberto Sangiovanni-Vincentelli.
p. cm. -- (Kluwer international series in engineering and
computer science; SECS 585)
Includes bibliographical references and index.
ISBN 978-1-4613-6959-2 ISBN 978-1-4615-4359-6 (eBook)
DOI 10.1 007/978-1-4615-4359-6
1. Embedded computer systems--Design and construction. 2. System design. 1.
Tabbara, Abdallah, 1968-II. Sangiovanni-Vincentelli, Alberto. III. Title. IV.
Series.
TK7895.E42 T33 2000
62l.39'16--dc21
00-062188
Copyright © 2000 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 2000
Softcover reprint of the hardcover lst edition 2000
AII rights reserved. No part ofthis publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical, photo
copying, recording, or otherwise, without the prior written permission of the
publisher, Springer Science+Business Media, LLC.
Printed on acid-free paper.
CONTENTS
LIST OF FIGURES ix
LIST OF TABLES xiv
PREFACE xv
1 Introduction and Background 1
1 INTRODUCTION 3
1.1 Motivation 4
1.2 Research Overview and Objective 8
1.3 This Work's Contribution 9
2 SYSTEM LEVEL DESIGN OF EMBEDDED SYSTEMS 11
2.1 The Application Domain, and Design Tools 11
2.2 Embedded System Design 11
2.3 System Level Design Validation of Embedded Systems 13
2.4 Co-simulation Validation Framework 14
2.5 Function Architecture Co-design Methodology 18
2.6 Reactive System Co-synthesis 23
2 Function I Architecture Optimization and Co-design 27
3 DESIGN REPRESENTATION 29
vi
3.1 Background 33
3.2 Novel Intermediate Design Representation 38
3.3 Proof of Concept 47
4 FUNCTION OPTIMIZATIONS 49
4.1 Optimization Methodology 49
4.2 Mathematical Framework for Control and Data Flow Analysis 51
4.3 The FFG Data Flow and Control Optimization Algorithm 65
4.4 Properties of The FFG Optimization Algorithm 74
4.5 Tree vs. Shared DAG Form of the FFG 79
4.6 The Backdrop: Related Work in Optimization 80
4.7 Future Directions 81
5 FUNCTION I ARCHITECTURE OPTIMIZATIONS 85
5.1 Function I Architecture Representation: AFFG 86
5.2 Function Architecture Co-design in the Macro-Architecture 87
5.3 Operation Motion in the AFFG 88
5.4 Other Constraint-Driven Optimization Techniques 101
5.5 Optimizing the Function to be Mapped onto the Macro-
Architecture 102
5.6 Function Architecture Co-design in the Micro-Architecture 113
5.7 Future Directions 116
6 ARCHITECTURAL OPTIMIZATIONS 121
6.1 Target Architectural Organization 121
6.2 CFSM Network Architecture: SHIFT 126
6.3 Architectural Modeling 126
6.4 Mapping the AFFG onto SHIFT 132
6.5 Architecture Dependent Optimizations 135
6.6 Future Directions 145
7 HARDWARE/SOFTWARE CO-SYNTHESIS AND
ESTIMATION 147
7.1 Hardware/Software Co-synthesis 147
7.2 Software CFSM Representation: The S-graph 148
7.3 Polis Approach to Software Synthesis 150
Contents vii
7.4 Polis Approach to Hardware Synthesis 154
7.5 Optimization and Co-design Guiding Co-Synthesis 154
7.6 The Real Time Operating System 155
7.7 Interfacing Polis to Commercial RTOSs 158
7.8 Optimizing the RTOS 163
7.9 Measuring the Final Implementation Cost 165
7.10 Software Estimation 166
7.11 Hardware Estimation 174
3 Overall Co-design Flow, Results, Conclusions, and the Future 175
8 FUNCTION I ARCHITECTURE OPTIMIZATION AND
CO-DESIGN FLOW 177
8.1 Inter-CFSM Optimizations 177
8.2 Functional Decomposition 180
8.3 A Comprehensive Function Architecture Co-design and Op-
timization Flow 183
8.4 Software Implementation 185
9 SYNTHESIS RESULTS 189
9.1 A Communications Domain Application Example: An ATM
Server 190
9.2 An Automotive Dashboard Controller 200
9.3 Results on Data-rich Control Designs 203
10 CONCLUSIONS AND FUTURE RESEARCH
OPPORTUNITIES 211
INDEX 217
REFERENCES 235
A C-LIKE INTERMEDIATE FORMAT (CLIF) FOR DESIGN
REPRESENTATION 245
LIST OF FIGURES
Chapter 1
1.1 Future Designs: The PicoRadio and Its Design Challenges
(Courtesy Jan Rabaey, BWRC) 5
1.2 New Design Start Crisis: The Productivity Gap 6
Chapter 2
2.1 Major Roles in Embedded System Design 12
2.2 Accuracy and Throughput Trade-offs in HW/SW Co-simulation 16
2.3 Estimation-based High Level HW/SW Co-simulation 17
2.4 Function Architecture Co-design Methodology 19
2.5 Methodology for Embedded System Architecture Exploration
(from [5]) 20
2.6 Reactive System Co-synthesis 24
2.7 Data Flow Optimization and the CDFG Representation 24
Chapter 3
3.1 Unifying Intermediate Design Representation for Co-design 30
3.2 Applications and Platforms (from [42]) 31
3.3 System Representation in Polis: A Network of CFSMs 35
3.4 Simple Esterel Design Example 36
3.5 Our Proposed Unifying Task Representation for Function /
Architecture Co-design 40
3.6 Simple FFG and Its CLIP Representation 42
3.7 EFSM in FFG Tree Form: A Simple Example 45
3.8 EFSM in FFG Shared DAG Form: A Simple Example 46
3.9 Simple Design Example in CLIP 47
3.10 Compilation Code Size Result With and Without FFG Level
Optimizations 48
x
Chapter 4
4.1 Lattice of Subsets of Definitions (from [2]) 54
4.2 Reaching Definitions: MFP vs. JOP 58
4.3 An Irreducible Flow Graph 61
4.4 Reached Uses 68
4.5 Available Expressions 70
4.6 False Branch Pruning 71
4.7 Redundancy Addition 72
Chapter 5
5.1 Function Architecture Co-design 85
5.2 Architecture Dependent Representation 87
5.3 Illustrative Example (from [68]) 92
5.4 Result After Dead Addition 94
5.5 Result After Available Elimination 95
5.6 Bayesian Belief Network for Party Location 97
5.7 Belief Network for the Knoop Example (Courtesy Microsoft
Research) 99
5.8 Optimization with ROM 101
5.9 State in the AFFG 107
5.10 State Frontier and Register Allocation 110
5.11 Operator Strength Reduction, and Instruction Selection 116
5.12 Flexibilities: Illustrative Example 119
Chapter 6
6.1 Abstract Target Platform 123
6.2 A Simple CFSM 124
6.3 Task Level Control and Data Flow Organization 125
6.4 CFSM Network Architecture in SHIFT 127
6.5 Moving Control into the Datapath 138
6.6 Sharing Computations During the AFFG to SHIFT Mapping 139
6.7 Multiplexing Computation Inputs 141
Chapter 7
7.1 Our Optimization and Synthesis Flow 147
7.2 The Polis Design Flow 148
7.3 The CFSM of the Seat Belt Alarm Controller 151
7.4 The S-graph of the Seat Belt Alarm Controller 152
7.5 C Code for the Seat Belt Alarm Controller 153
7.6 Communication Mechanism Between CFSMs 157
7.7 RTOS Synthesis and Evaluation in Polis 158
7.8 Proto typing Platform 161
7.9 A Simple S-graph Annotated with Execution Cost 167
7.10 Parameter Extraction Flow 168
Chapter 8
8.1 Overall Co-design Process: Concept Flow 178
8.2 Overall Co-design Process: Concrete Flow 184
8.3 Overall Co-design Process: Toolset Flow 186
Chapter 9
9.1 Operational View of the Buffer Inside the ATM Server 190
9.2 A High Level Description of the ATM Server 191
9.3 Internal Architecture of the ATM VPN Server 192
9.4 Elaborating ALGORITHM and SUPERVISOR Modules 194
9.5 Automotive Dashboard Controller (from [5]) 201
9.6 Software Benchmarks 204
Chapter 10
10.1 Function / Architecture Optimization and Co-design for Plat-
forms 212
Appendix A