Fully Integrated CMOS Power Amplifier

192 Pages·2006·3.57 MB·English

Fully Integrated CMOS Power Amplifier
Gang Liu
Electrical Engineering and Computer Sciences
University of California at Berkeley
Technical Report No. UCB/EECS-2006-162
http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-162.html
December 6, 2006
Copyright © 2006, by the author(s).
All rights reserved.

Permission to make digital or hard copies of all or part of this work for
personal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that copies
bear this notice and the full citation on the first page. To copy otherwise, to
republish, to post on servers or to redistribute to lists, requires prior specific
permission.
Fully Integrated CMOS Power Amplifier
by
Gang Liu
B.E. (Tsinghua University) 1998

A dissertation submitted in partial satisfaction of the
requirements for the degree of
Doctor of Philosophy
in
Engineering - Electrical Engineering and Computer Sciences
in the
GRADUATE DIVISION
of the
UNIVERSITY OF CALIFORNIA, BERKELEY

Committee in charge:
Professor Ali M. Niknejad, Co-chair
Professor Tsu-Jae King Liu, Co-chair
Professor Peidong Yang

Fall 2006
The dissertation of Gang Liu is approved:

-----------------------------------------------------------------------------------
Co-chair Date

-----------------------------------------------------------------------------------
Co-chair Date

-----------------------------------------------------------------------------------
Date

UNIVERSITY OF CALIFORNIA, BERKELEY
Fall 2006
Fully Integrated CMOS Power Amplifier
Copyright 2006
by
Gang Liu
Abstract

Fully Integrated CMOS Power Amplifier
by
Gang Liu
Doctor of Philosophy in Electrical Engineering and Computer Sciences
University of California, Berkeley
Professor Ali M. Niknejad, Co-chair
Professor Tsu-Jae King Liu, Co-chair

Today’s consumers demand wireless systems that are low-cost, power efficient,
reliable and have a small form-factor. High levels of integration are desired to reduce
cost and achieve compact form factor for high volume applications. Hence the long term
vision or goal for wireless transceivers is to merge as many components as possible, if
not all, to a single die in an inexpensive technology. Therefore, there is a growing
interest in utilizing CMOS technologies for RF power amplifiers (PAs). Although
several advances have been made recently to enable full integration of PAs in CMOS, it
is still among the most difficult challenges in achieving a truly single-chip radio system
in CMOS. This is exacerbated by supply voltage reduction due to CMOS technology
scaling and on-chip passive losses due to the conductive substrate used in deep
submicron CMOS processes.
1
Efficiency is one of the most important metrics in the design of power amplifiers.
Conventional designs give maximum efficiency only at a single power level, usually near
the maximum rated power for the amplifier. As the output power is backed off from that
single point, the efficiency drops rapidly. However, power back-off is inevitable in
today’s wireless communication systems.
To date, there has been relatively little research on the design of a CMOS PA
targeting good average efficiency. A new transformer combining architecture, which is
suitable in designing highly efficient PAs in CMOS processes, is proposed to address this
issue. A prototype was implemented with only thin-oxide transistors in a 0.13-µm RF-
CMOS process to demonstrate the concept. Experimental results validate our concept
and demonstrate the feasibility of highly efficiency, fully integrated power amplifiers in
CMOS technologies.

----------------------------------------------------------
Professor Ali M. Niknejad
Dissertation Committee Co-chair

----------------------------------------------------------
Professor Tsu-Jae King Liu
Dissertation Committee Co-chair
2
Contents

Chapter 1: Introduction.......................................................................................................1
1.1 Recent developments of wireless communication technologies...............................1
1.2 Motivation.................................................................................................................6
1.3 Overview of the work and its contribution...............................................................9
1.4 Organization of the thesis.......................................................................................11
1.5 References...............................................................................................................12

Chapter 2: Fundamentals of Power Amplifiers................................................................16
2.1 An overview of classifications and specifications of PAs......................................16
2.1.1 Class-A, AB, B, and C power amplifiers.........................................................16
2.1.2 Class-D power amplifiers................................................................................18
2.1.3 Class-E power amplifiers.................................................................................18
2.1.4 Class F power amplifiers.................................................................................20
2.1.5 Class-G and Class-H power amplifiers............................................................20
2.1.6 Class-S power amplifiers.................................................................................21
2.1.7 Hybrid class power amplifiers.........................................................................21
2.1.8 Performance metrics of power amplifiers........................................................22
2.2 Efficiency of Power Amplifiers..............................................................................22
2.3 Linearity of Power Amplifiers................................................................................30
2.3.1 AM-AM Conversion........................................................................................31
2.3.2 AM-PM Conversion.........................................................................................33
2.3.3 Adjacent Channel Power Ratio (ACPR)..........................................................34
2.3.4 Spectral MASK................................................................................................35
2.3.5 Error Vector Magnitude (EVM)......................................................................36
2.3.6 Linearization Techniques.................................................................................38
2.4 Summary.................................................................................................................39
2.5 References...............................................................................................................39

Chapter 3: CMOS Technology for RF Power Amplifiers................................................42
3.1 Prevalent Technologies for RF Power Amplifiers..................................................42
3.1.1 GaAs HBT Technology...................................................................................42
3.1.2 GaAs MESFET Technology............................................................................44
3.1.3 GaAs HEMT Technology................................................................................45
3.1.4 Si CMOS Technology......................................................................................48
3.1.5 SiGe HBT Technology....................................................................................51
3.1.6 Si LDMOS Technology...................................................................................53
3.2 Comparisons among Prevalent Technologies.........................................................54
3.2.1 Substrate...........................................................................................................56
i
3.2.2 Backside Vias...................................................................................................57
3.2.3 Passives............................................................................................................58
3.2.3 Device characteristics......................................................................................61
3.2.4 Manufacturing Cost.........................................................................................64
3.2.5 Integration........................................................................................................66
3.2.6 Availability & Capacity...................................................................................66
3.3 Trends of Supply Voltages for Portable Devices....................................................67
3.4. Limits of CMOS and the Impact of Scaling..........................................................72
3.4.1 Device Scaling.................................................................................................72
3.4.2 Starting Materials.............................................................................................74
3.4.3 Metal Stack Scaling.........................................................................................74
3.5 Summary.................................................................................................................75
3.6 References...............................................................................................................76

Chapter 4: Generating High Power with Low Voltage Devices.......................................80
4.1 Series Power Combining.........................................................................................80
4.1.1 Cascode Configuration.....................................................................................80
4.1.2 Totem-Pole Technique.....................................................................................83
4.1.3 Stacked Transistors Amplifier.........................................................................84
4.2 Parallel Combining.................................................................................................85
4.2.1 Transformer Based Power Combining.............................................................85
4.2.2 Transmission Line Based Power Combining...................................................88
4.3 Proposed Power Combiner.....................................................................................94
4.3.1 Power Combining Transformer.......................................................................94
4.4 Summary...............................................................................................................114
4.5 References.............................................................................................................115
Chapter 5. The Power Combining Transformer Design.................................................118
5.1 Impedance Transformation...................................................................................118
5.1.1 LC Resonant Matching Network...................................................................119
5.1.2 Transformer Matching Network....................................................................123
5.2 Design Considerations of Transformers for Power Amplifiers............................129
5.2.1 Low Impedance Inductor Design...................................................................131
5.2.2 Low Turn Ratio Transformer Design............................................................136
5.3 Design and Implementation of the Proposed Transformer...................................139
5.4 Discussions and Summary....................................................................................143
5.5 References.............................................................................................................146

Chapter 6. A Fully Integrated CMOS Power Amplifier with Average Efficiency
Enhancement...................................................................................................................148
6.1 Design of the Prototype........................................................................................149
6.1.1 Features of the CMOS Process......................................................................149
6.1.2 PA Architecture.............................................................................................149
6.1.3 Power Combining..........................................................................................150
6.1.4 Pseudo-Differential Pair.................................................................................151
6.1.5 Transconductor Design..................................................................................152
6.1.6 Cascode Transistor Design............................................................................155
ii
6.1.7 Output Matching Network – Transformer Power Combiner.........................157
6.1.8 Stability..........................................................................................................160
6.2 Layout Considerations..........................................................................................162
6.2.1 Transconductor Layout..................................................................................162
6.2.2 Cascode Transistor Layout............................................................................165
6.3 The CMOS Prototype...........................................................................................166
6.4 Experimental Results............................................................................................170
6.4.1 CW Signal Test..............................................................................................171
6.4.2 Modulated Signal Test...................................................................................174
6.5 Summary...............................................................................................................177
6.6 References.............................................................................................................177

Chapter 7. Conclusion.....................................................................................................179
7.1 Thesis Summary....................................................................................................179
7.2 Possible Future Directions....................................................................................181

iii