FPGA Based VGA Driver and Arcade Game

37 Pages·2010·1.49 MB·English

FPGA BASED VGA DRIVER
AND ARCADE GAME
ARMANDAS JARUSAUSKAS
THIRD YEAR INDIVIDUAL PROJECT
2009/2010
SCHOOL OF ENGINEERING & DESIGN
UNIVERSITY OF SUSSEX
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Abstract
Field­Programmable Gate­Array (FPGA) technology is gaining popularity among Application­Specific 
Integrated Circuit (ASIC) designers. Ease of development and maintenance makes FPGAs an attractive 
solution to many speed and efficiency­critical applications. The purpose of this project is to explore the 
world of FPGAs by implementing an arcade game on top of a VGA driver. The project was implemented 
on Xilinx Spartan­3E development board using VHDL hardware description language.
The project was started by learning VHDL as well as familiarising with the Spartan­3E development 
board and Xilinx ISE WebPACK design software. A number of simple applications were developed in 
order to comfortably proceed on to investigation of working principles of a VGA driver. It turned out 
that the synchronisation logic was rather trivial and that the custom implementation would not add 
much value to the project.
VHDL implementation of the classic Pong game was the first major task of the project. Plong, as it was 
named, is a two­player game, where each player tries to to hit a ball towards the opponent. A number 
of basic features, such as acceleration of the ball, sound output and textual information display, have 
been implemented. As this game was developed in the early stage of the project, complexity was 
consciously avoided.
The objectives the second game, on the other hand, were focused on technical features and other 
improvements. Still monochrome images were exchanged for colourful animations, sound output was 
made more sophisticated by adding a tune player, Nintendo game pads replaced on­board switches as a 
user input interface and a number of other modules were developed. The theme was chosen to 
resemble the Space Invaders game, but all graphic elements were designed from scratch.
To make the project more complete and self contained, the two games were combined into a single 
application, with a menu screen to allow user to choose which game to play.
Lastly, an adaptor board, for connecting NES game pads to the development board, was designed and 
built. It facilitates the communication between the controllers and the FPGA. The board also hosts a 
piezoelectric buzzer for sound output and a reset switch.
The project was complete and fully functional before the deadline. While there is still a lot of room for 
improvement, all set objectives, and more, were met.
Statement of originality
I hereby declare that this report is my own work and to the best of my knowledge it contains no
materials previously published or written by another person, or which have been accepted for the
award of any degree or diploma at any educational institution, except where due acknowledgement is
made in the report itself.
Acknowledgements
First supervisor: Dr Ahmet Aydin
Second supervisor: Dr Christopher Harland
I would like to thank the following people for all the help and support:
• Ahmet Aydin for his time and support during the project and for letting me borrow the FPGA
development board.
• Sam Beardsmore-Rust for general support and help with project proposal.
• Philip Watson for 100-pin connector design files and other help.
• Martin Nock for help with PCB manufacture.
• David Smith, from the mechanical workshop, for his excellent work on a plastic case for my
adaptor board.
Table of Contents
1 INTRODUCTION 9
1.1 About this report..............................................................................................................9
1.2 Project aims and plan.......................................................................................................9
2 BACKGROUND 9
2.1 Field-Programmable Gate Arrays....................................................................................9
Xilinx versus Altera..........................................................................................................................9
2.2 Hardware description languages...................................................................................10
VHDL...............................................................................................................................................10
Digital systems theory..............................................................................................................10
Other HDLs.....................................................................................................................................10
2.3 Development board........................................................................................................10
2.4 VGA...................................................................................................................................11
Hardware........................................................................................................................................11
Timing.............................................................................................................................................11
2.5 Nintendo controllers......................................................................................................12
2.6 Principles of game implementation..............................................................................12
Logic blocks....................................................................................................................................12
Objects............................................................................................................................................12
3 IMPLEMENTATION 13
3.1 VGA...................................................................................................................................13
Code................................................................................................................................................13
Results............................................................................................................................................13
3.2 NES controller interface.................................................................................................14
Code................................................................................................................................................14
Results............................................................................................................................................14
3.3 Graphics...........................................................................................................................14
Storing images...............................................................................................................................15
Getting the pixels...........................................................................................................................15
Moving images...............................................................................................................................16
Colour image storage....................................................................................................................16
3.4 Text generation...............................................................................................................17
Font.................................................................................................................................................17
Grid.................................................................................................................................................17
3.5 Binary to BCD conversion...............................................................................................17
Theory.............................................................................................................................................17
VHDL implementation...................................................................................................................18
3.6 Sound...............................................................................................................................18
Frequency generator.....................................................................................................................18
Sound ROM....................................................................................................................................18
Player..............................................................................................................................................18
4 PONG 19
4.1 Structure..........................................................................................................................19
4.2 Graphics...........................................................................................................................19
Main logic.......................................................................................................................................19
Paddle logic....................................................................................................................................20
Ball logic.........................................................................................................................................20
Scores.............................................................................................................................................20
4.3 Sounds & User input.......................................................................................................21
Sounds............................................................................................................................................21
User input.......................................................................................................................................21
5 SPACE SHOOTER 21
5.1 Gameplay.........................................................................................................................21
5.2 Graphics...........................................................................................................................22
Main logic.......................................................................................................................................22
Aliens..............................................................................................................................................22
Spaceship and missile...................................................................................................................22
Explosion logic...............................................................................................................................22
Score and level display..................................................................................................................23
6 COMPLETING THE PROJECT 23
6.1 Game selection menu.....................................................................................................23
6.2 Combining the applications...........................................................................................23
7 ADAPTOR BOARD 23
7.1 Reverse engineering the controllers.............................................................................23
7.2 TTL / CMOS level conversion..........................................................................................24
FPGA to Shift register.....................................................................................................................24
Shift register to FPGA.....................................................................................................................24
7.3 Board design....................................................................................................................24
Schematic capture.........................................................................................................................24
PCB layout design..........................................................................................................................24
Manufacture...................................................................................................................................24
8 DISCUSSION 25
8.1 Issues...............................................................................................................................25
Pong ball acceleration...................................................................................................................25
Synchronisation problems............................................................................................................25
Adaptor board................................................................................................................................26
Binary-to-BCD conversion.............................................................................................................26
8.2 Further work...................................................................................................................26
9 CONCLUSION 26
REFERENCES 27
BIBLIOGRAPHY 27
APPENDIX A 28
Initial technical proposal....................................................................................................28
APPENDIX B 29
Project parts list...................................................................................................................29
APPENDIX C 30
Project plan..........................................................................................................................30
APPENDIX D 31
NES Controller: equivalent schematic diagram................................................................31
APPENDIX E 32
Python script for generating VHDL ROM from images.....................................................32
APPENDIX F 33
Adaptor board schematic diagram.....................................................................................33
APPENDIX G 34
Adaptor board PCB: top and bottom layer masks.............................................................34
APPENDIX H 35
Photographs.........................................................................................................................35
FPGA BASED VGA DRIVER
AND ARCADE GAME
and   milestones was created to give a rough 
1 INTRODUCTION estimate of duration of each part of the project.
1.1 About this report 2 BACKGROUND
This report covers the work done during the 
course of the project. An introduction to core  2.1 Field-Programmable Gate Arrays
concepts relating to the project is given in Chapter 
FPGAs are modern programmable logic devices 
2  section. Chapter  3  describes how the main 
that can be configured to perform any logic 
building blocks, used to create a game, were 
operation.
developed, while Chapters  4,  5  and  6  go into 
game­specific details. Design of an adaptor board,  An   FPGA   typically   contains   a   matrix   of 
connecting game pads to the development board,  programmable   elements,   also   known   as, 
is described in Chapter 7. Report is finished by  Configurable Logic Blocks (CLBs). CLBs contain 
discussing some of the issues experienced during  Look­Up Tables (LUTs), that can be used as logic 
the project, and Conclusion. or storage elements. The configuration data is 
stored in the memory.
Throughout the report, you will see notes like 
this: Spartan­3E series FPGAs, used in this project 
contain the following structures, as described in 
[1]:
Project - filename.vhd
• Configurable Logic Block  – logic and 
It is a pointer to a relative source file. It may be  basic storage elements are implemented 
helpful, if one needs to see the implementation  using the Look­UP Tables (LUTs).
details.
• Input/Output Block (IOB) – control the 
The report is accompanied by a printed VHDL  data flow between the I/O pins and 
code listing and a Compact Disc. The CD contains  internal logic of the device. LVTTL and 
all   the   relevant   material   in   digital   format,  LVCMOS  logic standards are supported 
including this report, VHDL code, scanned version  among others.
of engineering logbook and more.
• Block RAM  – memory used for data 
storage.   Organized   as   18kb   dual­port 
1.2 Project aims and plan blocks.
The aim of this project was to explore the  • Digital clock manager block – provides 
capabilities   of   modern   programmable   logic  management for clock signals.
devices while getting hands­on experience of 
FPGA development.
Xilinx versus Altera
The above definition is rather abstract and can be 
There   are   two   major   manufacturers   in   the 
hard to assess. For this purpose, a number of 
programmable logic business – Xilinx and Altera. 
objectives were set. The initial technical proposal 
Xilinx is a current market share leader, with Altera 
can be found in  Appendix A. Below, is the 
being a close second.
amended list of objectives.
The decision which one to choose should not be 
• Learn about FPGAs, development tools 
based on the architectural differences of the two 
and VHDL, start programming.
technologies. There are many more important 
• Produce a simple application, that uses a  aspects, such as device availability, overall price, 
VGA driver to display graphics on a  development   tools,   existence   of   Intellectual 
computer monitor. Property (IP) cores and educational material and 
so forth.
• Create a simple game.
Xilinx   Spartan­3E   development   boards   were 
• Create a more advanced game.
readily available at the university and, therefore, 
• Design some hardware. Xilinx technology was used for this project's 
implementation.
A plan, available in Appendix B, with objectives 
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FPGA BASED VGA DRIVER
AND ARCADE GAME
2.2 Hardware description languages Other HDLs
As with the FPGAs, there are two predominant 
VHDL hardware description languages – VHDL and 
Verilog.
“VHDL   is   a   language   for   describing   digital 
electronic systems. It arose out of the United  And just like with FPGAs, HDL usage is more a 
States government's Very High Speed Integrated  matter of preference. Capabilities are pretty much 
Circuit (VHSIC) program. In the course of this  equal. The difference lies in how the hardware is 
program, it became clear that there was a need for  described. Verilog  is somewhat similar to C 
a standard language for describing the structure  programming language, whereas VHDL is based 
and function of Integrated Circuits (ICs). Hence  on Ada.
the   VHSIC   Hardware   Description   Language 
According to Wakerly [3], it is best to “learn one 
(VHDL) was developed” (Ashenden, 1996) [2].
well and, only if necessary, tackle the other later”.
VHDL became an IEEE standard in 1987. Several 
revisions have been done since then.
2.3 Development board
VHDL can be used not only to describe digital 
hardware but also to create test benches for 
testing the designs.
VHDL supports many built­in and user­defined 
data types. Some of most often used are
• std_logic (single bit)
• std_logic_vector (bit vector)
• numerical types such as integer
• arrays, enumerated lists, etc.
Unlike imperative programming languages, such 
as C++, VHDL statements are concurrent (i.e. run 
in parallel). Concurrency is very useful in HDLs, as 
it resembles the way hardware works. Sequential 
statements can be implemented using a special 
FIGURE 2.1: SPARTAN-3E BOARD
construct called process.
The development board used in this project is 
Every VHDL design must have an entity and an 
shown in Figure 2.1. It uses a Spartan­3E series 
architecture. The Entity contains a declaration of 
FPGA (model XC3S500E) with the following 
I/O ports while the actual design code resides in 
characteristics [1]:
the architecture part.
• 500,000 system gates, making over ten 
Signals declared in the entity are referred to as 
thousand equivalent logic cells.
external and are usually tied to I/O pins on the 
FPGA. The mapping of signals to pins is done in  • 20 RAM blocks totalling 360kb of memory.
the User Constraints File (UCF).
• 20 dedicated multipliers.
Internal signals are declared in the architecture 
• A maximum of 232 I/O pins.
body and cannot be connected to the outside 
world. The board has a 15­pin D­subminiature connector 
to plug in a VGA monitor.
Digital systems theory Also, an on­board 100­pin expansion port is used 
to connect an adaptor board. Full list of features 
VHDL is a good example of practical application of 
can be found in the user guide [4].
digital circuit theory. Many of the basic concepts, 
such as gate and register­transfer level design, 
combinational logic and finite state machines have 
been used throughout the project.
10