Formal Equivalence Checking and Design Debugging

237 Pages·1998·6.778 MB·English

by  Shi-Yu Huang, Kwang-Ting (Tim) Cheng (auth.)

FORMAL EQUIVALENCE CHECKING
AND
DESIGN DEBUGGING
FRONTIERS IN ELECTRONIC TESTING
Consulting Editor
Vishwani D. Agrawal
Books in the series:
On-Line Testing for VLSI
M. Nicolaidis, Y. Zorian
ISBN: 0-7923-8132-7
Defect Oriented Testing for CMOS Analog and Digital Circuits
M. Sachdev
ISBN: 0-7923-8083-5
Reasoning in Boolean Networks: Logic Synthesis and Verification Using
Testing Techniques
W. Kunz, D. Stoffel
ISBN: 0-7923-9921-8
Introduction to IDDQ Testing
S. Chakravarty, P.J. Thadikaran
ISBN: 0-7923-9945-5
Multi-Chip Module Test Strategies
¥. Zorian
ISBN: 0-7923-9920-X
Testing and Testable Design of High-Density Random-Access Memories
P. Mazumder, K. Chakraborty
ISBN: 0-7923-9782-7
From Contamination to Defects, Faults and Yield Loss
J.B. Khare, W. Maly
ISBN: 0-7923-9714-2
Efficient Branch and Bound Search with Applications to
Computer-Aided Design
X.Chen, M.L. Bushnell
ISBN: 0-7923-9673-1
Testability Concepts for Digital ICs: The Macro Test Approach
F.P.M. Beenker, R.G. Bennetts, A.P. Thijssen
ISBN: 0-7923-9658-8
Economics of Electronic Design, Manufacture and Test
M. Abadir, A.P. Ambler
ISBN: 0-7923-9471-2
IDDQ Testing of VLSI Circuits
R. Gulati, C. Hawkins
ISBN: 0-7923-9315-5
FORMAL EQUIVA LENCE CHECKING
AND
DESIGN DEBUGGING
by
Shi-Yu Huang
National Semiconductor Corporation
and
Kwang-Ting (Tim) Cheng
0/
University California, Santa Barbara
~.
"
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication
Huang, Shi-Yu, 1965-
Formal equivalence checking and design debugging / by Shi-Yu Huang and
Kwang-Ting (Tim) Cheng
p. cm.
Includes bibliographical references and index.
ISBN 978-1-4613-7606-4 ISBN 978-1-4615-5693-0 (eBook)
DOI 10.1007/978-1-4615-5693-0
1. Integrated circuits-- Verification. 2. Electronic circuit design--Data processing.
3. Application specific integrated circuits--Design and construction.
I. Cheng, Kwang-Ting, 1961- 11. Title.
TK7874.H82 1998
621.3815--dc21 98-23993
CIP
Copyright <0 1998 Springer Science+Business Media New York. Second Printing 2002.
Originally published by Kluwer Academic Publishers, New York in 1998
Softcover reprint of the hardcover 1s t edition 1998
This printing is a digital duplication of the original edition.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher, Springer
Science+Business Media, LLC
Printed on acid-free paper.
FORMAL EQUIVALENCE CHECKING
AND
DESIGN DEBUGGING
CONTENTS
Foreword xi
Preface xvii
Chapter 1 Introduction 1
1.1 Problems of Interest ......................................................................................... 1
1.1.1 Equivalence Checking ........................................................................ 3
1.1.2 Design Error Diagnosis and Correction .............................................. 8
1.2 Organization ................................................................................................... 10
PART I EQUIVALENCE CHECKING
Chapter 2 Symbolic Verification 17
2.1 Symbolic Verification by FSM TraversaL .................................................... 17
2.2 Implicit State Enumeration by BDD .............................................................. 19
2.2.1 Set Representation ............................................................................ 20
2.2.2 Input/Output Relation ....................................................................... 21
2.2.3 Transition Relation ........................................................................... 23
2.2.4 Next-State Computation ................................................................... 25
2.2.5 Complete Flow ......................................................................... , ........ 26
2.2.6 Error Trace Generation ..................................................................... 28
2.3 Speed-up Techniques ..................................................................................... 30
2.3.1 An Efficient Method for Constructing Transition Relation ;. ............ 30
2.3.2 Reduction on Image Computation .................................................... 33
2.3.3 Reduction on Reachable State Computation .................... , ............... 36
2.4 Summary ........................................................................................................ 37
Chapter 3 Incremental Verification for Combinational Circuits 39
3.1 Substitution-Based Algorithms ...................................................................... 39
3.1.1 Brand's Algorithm Using ATPG ....................................................... 39
Pairing up candidate pairs ................................................................ 41
Pruning the miter incrementally ....................................................... 42
Checking the equivalence of primary outputs .................................. 44
3.1.2 Enhancement by Local BDD ....................................................... , .... 44
Constructing BDDs using a dynamic support .................................. 46
Experimental results ......................................................................... 48
3.2 Learning-Based Algorithms ...................................................................... :. ... 50
3.2.1 Recursive Learning ....................................... , ............................. :. .... 50
Vlll
3.2.2 Verification Flow Using Recursive Learning .................................... 51
3.3 Transformation-Based Algorithm .................................................................. 53
3.3.1 Identifying Dissimilar Region .......................................................... 53
3.3.2 Similarity Enhancing Transformation (SET) .................................... 55
3.4 Summary ........................................................................................................ 57
Chapter 4 Incremental Verification for Sequential Circuits 61
4.1 Definition of Equivalence .............................................................................. 62
:4.1.1 Equivalence of Circuits With A Reset State ..................................... 62
"4.1.2 Equivalence of Circuits Without A Reset State ................................ 62
Sequential Hardware Equivalence .................................................... 63
Safe Replaceability ........................................................................... 65
Three-Valued Safe Replaceability .................................................... 66
Three-Valued Equivalence ................................................................ 67
4.1.3 Comparison of Definitions ................................................................ 67
4.2 Methodology .................................................................................................. 72
4.2.1 Checking Three-Valued Safe Replaceability .................................... 73
4.2.2 Checking Reset Equivalence ............................................................. 74
4.2.3 Checking Three-Valued Equivalence ................................................ 76
4.3 The Speed-Up Techniques ............................................................................. 76
4.3.1 Test Generation with Breadth-First-Search ...................................... 77
4.3.2 Exploring the Structural Similarity ................................................... 79
4.3.3 Identifying Equivalent Flip-Flop Pairs ............................................. 80
4.4 Experimental Results ..................................................................................... 84
4.5 Summary ........................................................................................................ 86
4.6 Appendix ........................................................................................................ 87
Chapter-S AQUILA: A Local BDD-based Equivalence Verifier 91
5.1 Overall Flow .................................................................................................. 91
5.2 Two-Level Inductive Algorithm ..................................................................... 93
5.2.1 .Second-Level Assume-And-Then-Verify ......................................... 95
5.3 Symbolic Backward Justification ................................................................... 97
5.3.1 Partial Justification .......................................................................... 100
5.3.2 An Example .................................................................................... 102
5.4 Experimental Results ................................................................................... 105
5.5 Summary ...................................................................................................... 107
Chapter 6 Algorithm for Verifying Retimed Circuits 111
6.1 Introduction .................................................................................................. 111
6.2 Pre-Processing Algorithm ............................................................................ 113
6.2.1 Signature Computation ................................................................... 115
ix
6.2.2 Deriving Candidate Delayed-Equivalent Pairs ............................... 115
6.2.3 Delay Compensation ....................................................................... 117
6.3 Experimental Results ................................................................................... 118
6.4 Summary ...................................................................................................... 121
Chapter 7 RTL-to-Gate Verification 123
7.1 Introduction .................................................................................................. 123
7.2 Don't Care Modeling ................................................................................... 125
7.3 Integration with FSM Traversal ................................................................... 127
7.3.1 Computing a Subset of Unreachable States .................................... 128
7.3.2 Incremental Verification with Don't Cares ..................................... 130
7.4 Overall Flow for RTL-to-Gate Verification ................................................. 132
7.5 Experimental Results ................................................................................... 132
7.6 Summary ...................................................................................................... 136
PART II LOGIC DEBUGGING
Chapter 8 Introduction to Logic Debugging 139
8.1 Introduction .................................................................................................. 139
8.2 Symbolic Approach ..................................................................................... 141
8.2.1 Search for Error Locations .............................................................. 142
Single-fix function computation .............................. ,. ...................... 143
8.2.2 Correction by Re-synthesis ............................................................. 144
8.2.3 Generalization ................................................................................. 144
Output partitioning ......................................................................... 145
Multiple signal re-synthesis ............................................................ 145
8.3 Simulation-Based Approach ........................................................................ 146
8.3.1 Cone Intersection .................................................................. ;.~ ....... 147
8.3.2 Filter Based on Sensitization .......................................................... 148
8.3.3 Back Propagation ............................................................................ 150
8.3.4 Enhancement with Observability Measure ..................................... 153
8.4 Structural Approach ..................................................................................... 154
8.5 Summary ...................................................................................................... 156
Chapter 9 ErrorTracer: Error Diagnosis by Fault Simulation 159
9.1 Introduction .................................................................................................. 159
9.2 Basic Terminology ....................................................................................... 160
9.3 Single Error Diagnosis ................................................................................. 161
9.3.1 Correctability .................................................................................. 161
9.3.2 The Algorithm for Single Error Diagnosis ..................................... 162
x
9.3.3 Correctability Check via Fault Simulation ..................................... 163
9.4 Multiple Error Diagnosis ............................................................................. 165
9.4.1 k-Correctability ............................................................................... 166
9.4.2 A Two-Stage Algorithm for Diagnosing Multiple Errors ............... 167
9.5 Experimental Results ................................................................................... 168
9.6 Summary ...................................................................................................... 173
Chapter 10 Extension to Sequential Error Diagnosis 175
10.1 Introduction .................................................................................................. 175
10.2 Diagnosing Sequential Circuits ................................................................... 176
10.2.1 Correctability ................................................................................. 176
10.2.2 The Necessary and Sufficient Condition ....................................... 177
10.2.3 Correctability Check via Fault Simulation .................................... 180
10.2.4 Generalization for Multiple Errors ................................................ 181
10.3 Experimental Results ................................................................................... 182
10.3.1 Results of Diagnosing Single-error Circuits ................................. 183
10.3.2 Results of Diagnosing Double-Error Circuits ............................... 185
10.3.3 Challenges ..................................................................................... 186
10.4 Summary ...................................................................................................... 187
Chapter 11 Incremental Logic Rectification 189
11.1 Preliminaries ................................................................................................ 190
11.1.1 Definitions ..................................................................................... 190
11.1.2 Single Signal Correctable Circuit .................................................. 190
11.2 Incremental Logic Rectification .................................................................. 192
11.2.1 Error Region Pruning .................................................................... 192
11.2.2 Symbolic Partial Correction .......................................................... 193
11.2.3 Single-Gate Correction Criterion .................................................. 197
11.2.4 The Algorithm ............................................................................... 199
11.3 A Divide and Conquer Heuristic ................................................................. 200
11.3.1 Pure Structural Approach Based on Back-Substitution ................ 201
11.4 Experimental Results ................................................................................... 204
11.5 Summary ...................................................................................................... 209
Bibliography 211
Index 223
Foreword
The world is increasingly dependent on electronic systems. Electronic
systems have requirements on speed, cost, power, reliability, and on the
correctness of their functioning. Of these requirements functional
correctness is the most fundamental requirement because the speed and
reliability of an incorrectly functioning electronic system is of no interest.
To function correctly circuits must be designed, implemented and manufac
tured correctly. Verifying functional correctness is also becoming the
single largest bottleneck in the design process and to understand where that
time and effort is going it will be useful to further explain the nature of
these verification problems.
Given a specification of the functionality of an integrated circuit (IC),
design verification is the verification that the design of an IC is consistent
with its specification. By the design of an IC we mean the description
which embodies the designer's intent. For example in a register-transfer
level (RTL) synthesis methodology, the design is initially captured as an
RTL model of the circuit in a hardware-description language (HDL). This
RTL model, typically coded in Verilog or VHDL, can be both simulated
and synthesized. The design verification process typically proceeds by
creating a simulation driver which produces simulation stimuli for the RTL
model and a simulation monitor which monitors the correctness of the
outputs. This basic structure of the simulation model, driver and monitor
has remained unchanged for well over a decade. Progress in simulation has
principally focused on either raising the level of abstraction of simulation
(e.g., from gate-level to RTL) or improving the speed of simulation (e.g.,
from interpreted to compiled or cycle-based). Much research effort has
gone into exploring ways to apply formal verification techniques, such as
model-checking, to the design verification problem, but to date the success
of formal design verification has been limited to niche applications.
Perhaps the most successful use of formal design verification techniques
will be in using formal models to augment and direct simulation. Be that as