Flash Memories: Economic Principles of Performance, Cost and Reliability Optimization

287 Pages·2014·10.642 MB·English

by  Detlev Richter (auth.)

Springer Series in Advanced Microelectronics 40
Detlev Richter
Flash Memories
Economic Principles of Performance,
Cost and Reliability Optimization
Springer Series in Advanced Microelectronics
Volume 40
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Dr. Kiyoo Itoh, Kokubunji-shi, Tokyo, Japan
Prof. Thomas H. Lee, Stanford, CA, USA
Prof. Takayasu Sakurai, Minato-ku, Tokyo, Japan
Prof. Willy M. C. Sansen, Leuven, Belgium
Prof. Doris Schmitt-Landsiedel, Munich, Germany
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Detlev Richter
Flash Memories
Economic Principles of Performance,
Cost and Reliability Optimization
123
Detlev Richter
Instituteof Technical Electronics
Technical University ofMunich
Munich
Germany
ISSN 1437-0387
ISBN 978-94-007-6081-3 ISBN 978-94-007-6082-0 (eBook)
DOI 10.1007/978-94-007-6082-0
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To Svea and Annett
Preface
• System development and optimization is an iterative process of technical and
commercial decisions between hardware and software solutions based on dif-
ferentarchitecturesandconcepts.Decisionsarebasedontechnicalspecification
of the current product generation while often they do not reflect the long-term
product roadmap. The long-term development roadmap of a memory product
familyhasasignificantinfluenceonsystemcostandsystemperformanceandon
the commercial success of a new memory-centric system family.
• Non–volatile solid-state memories changed the way how to interact with our
world. NAND flash became the enabling technology for portable storage. The
availability of solid-state non–volatile memories large enough and fast enough
for a certain application space is enabling year by year new commercial prod-
ucts in this application area.
• The NAND flash product roadmap doubles year-by-year the memory density
andoutperformsthe conservativepredictionsoftheITRS roadmap.Inthe past,
the read access of a memory cell through a NAND string of 32 cells was
commentedasachallengingandlessreliablememoryconcept.NANDflashwas
becoming the driver of the whole semiconductor memory industry. This book
willsystematicallyintroducecell,design,andalgorithmaspectsofNANDflash,
compare them to alternative solutions and make conclusions valid for flash
memories.
• Acomplexityfigureisintroducedtoillustratethechallengesalonganonvolatile
memorydevelopment.Performanceindicatorvaluesarecalculatedbasedonthe
introduced memory array model to reduce this complexity and derive quanti-
tative figures to guide performance, cost, and durability optimization of non-
volatile memories and memory-centric systems.
• A performance indicator methodology is developed and the main graphical
representationisbasedonperformanceandapplicationtrendlines.Thestrength
of this method is the quantitative judgment of different cell and array archi-
tectures. The methodology enables the opportunity to compensate insufficient
vii
viii Preface
marginsinthedurabilityparameters onsystemlevelbyincreasingothervalues
like memory density and program performance. The introduced model-based
performance indicator analysis is a tool set supporting iterative decision pro-
cesses for complex systems.
Important Notice Regarding the Use of this Thesis
Theinformationcontainedinthisworkmaydescribetechnicalinnovations,which
aresubjectofpatentsheldbythirdparties.Anyinformationgiveninthisworkisin
no form whatsoever an inducement to infringe any patent.
April 2013 Detlev Richter
Acknowledgments
The idea to describe all the different aspects—optimizing a complex nonvolatile
semiconductor-based systems—and to make an assessment of each method was
born during my employment time at Qimonda Flash GmbH.
During my time working as an independent technology consultant, I missed a
systematic analysisofall effects influencing anonvolatile system. The systematic
definition of each nonvolatile effect was the starting point to develop the non-
volatile memory lectures given at Technical University Munich.
My studies are focused to work out the dependencies between nonvolatile
memory key parameters within complex systems and translating them into
structured models. These performance models are part of nonvolatile memory
lectures to demonstrate the importance of certain hidden parameters for a com-
mercially successful product and system development roadmap.
A model-based approach is introduced and used to analyze the evolutionary
development of complex systems and to apply the key performance parameter
methodology to predict disruptive innovations for nonvolatile memories as the
most complex semiconductor devices with a regular structure and cutting-edge
lithography requirements.
I would like to thank Prof. Dr. rer. nat. Doris Schmitt-Landsiedel for sup-
porting, accompanying, and accepting this work.
Further thanks are due to:
Dr.AndreasKuxforsupport,suggestions,anddiscussionsforalmost12years;
Dr. Christoph Friederich for support, sharing new ideas especially on nonvol-
atile memories;
Dr.GertKoebernikforprogramming,testing,anddesigningflashalgorithmon
highest level;
AndreasTäuberforaproductivetimeworkingtogetheronembeddedDRAM’s,
on charge trapping, and on floating gate flash memory designs.
Dr. Thomas Kern, Dr. Josef Willer, Dror Avni, Shai Eisen, Asaf Shappir, and
Boaz Eitan for an intensive and innovative working time improving charge trap-
ping flash memories. Doris Keitel-Schulz, Dr. Markus Foerste, Dr. Jan Hayek,
Dr. Michael Specht, Johann Heitzer, and Rino Micheloni for the great support
duringmyproductinnovationtimes;Furtherthankstoallpeopleworkingonflash
memories during my times at Infineon Flash GmbH and Qimonda Flash GmbH.
ix
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Scope of Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Overview About the Structure. . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Fundamentals of Non-Volatile Memories . . . . . . . . . . . . . . . . . . . 5
2.1 Moore’s Law: The Impact of Exponential Growth. . . . . . . . . . . 5
2.1.1 History of Non-Volatile Floating-Gate Memories . . . . . . 5
2.1.2 Moore’s and Hwang’s Law . . . . . . . . . . . . . . . . . . . . . 7
2.1.3 History of Solid-State Storage: Cell and Application
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1.4 Memory Cell Classification . . . . . . . . . . . . . . . . . . . . . 9
2.2 Non-Volatile Storage Element: Cell Operation Modes . . . . . . . . 10
2.2.1 EEPROM: The Classical Two Transistor
Memory Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2 Single MOS Transistor: Electron Based
Storage Principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3 Operation Modes of Floating Gate MOSFET . . . . . . . . . 13
2.2.4 Flash Cell Operation Summary. . . . . . . . . . . . . . . . . . . 18
2.3 Non-Volatile Cell: Electron and Non-Electron Based. . . . . . . . . 19
2.3.1 Flash Cell: Floating Gate Technology . . . . . . . . . . . . . . 20
2.3.2 Flash Cell: Charge Trapping Technology. . . . . . . . . . . . 22
2.3.3 Two Bit per Cell Nitride ROM: Charge Trapping
Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.4 Non-Electron Based Cells: PCRAM, MRAM,
FeRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.5 Summary: Non-Volatile Cell . . . . . . . . . . . . . . . . . . . . 30
2.4 Flash Memory Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4.1 Array of Cells: Threshold Voltage Distributions. . . . . . . 32
2.4.2 NOR Array: Direct Cell Access . . . . . . . . . . . . . . . . . . 34
2.4.3 Virtual Ground NOR Array . . . . . . . . . . . . . . . . . . . . . 46
2.4.4 NAND Array: Indirect Cell Access. . . . . . . . . . . . . . . . 54
2.4.5 Summary: Flash Array Architecture . . . . . . . . . . . . . . . 62
xi