Flash ADCs PDF
Preview Flash ADCs
Department of Electrical and Computer Engineering Flash ADCs Vishal Saxena, Boise State University ([email protected]) © Vishal Saxena -1- Flash ADC Architecture V i • Reference ladder consists of 2N equal V FS 7 size resistors 7Δ • Input is compared 6 6Δ to 2N-1 reference 5 voltages r e 5Δ d o c • Massive parallelism n E 2Δ • Very fast ADC 1 architecture Δ • Latency = 1 T = 0 s D 1/f o 0 s • Throughput = f s • Complexity = 2N © Vishal Saxena -2- Thermometer Code V V FS i Strobe Thermometer code f s 0 1 1 1 2N-1 comparators © Vishal Saxena -3- Thermometer Code V V Thermometer code b b b FS i Strobe 2 1 0 f s 1 0 111 0 1 110 1 1 010 1 1 001 000 2N-1 1-of-n code comparators ROM encoder © Vishal Saxena -4- Flash ADC Challenges • V = 1.8 V DD • 10-bit → 1023 comparators • V = 1 V → 1 LSB = 1 mV FS • DNL < 0.5 LSB → V < 0.5 LSB os • 0.5 mV = 3-5 σ → σ = 0.1-0.2 mV • 2N-1 very large comparators • Large area, large power consumption • Very sensitive design • Limited to resolutions of 4-8 bits © Vishal Saxena -5- Flash ADC Challenges • DNL < 0.5 LSB • Large V relaxes FS offset tolerance x a m • Small V benefits , s FS o conversion speed (settling, linearity of building blocks) © Vishal Saxena -6- ADC Input Capacitance A 2 σ2 V Vth C 10 fF /μm2 th g WL • N = 6 bits → 63 comparators N (bits) # of comp. C (pF) in • V = 1 V → 1 LSB = 16 mV FS 6 63 3.9 • σ = LSB/4 → σ = 4 mV 8 255 250 • A = 10 mV·μm → L = 0.24 μm, VT0 10 1023 ??! W = 26 μm • Small V leads to large device sizes, hence large area and power os • Large comparator leads to large input capacitance, difficult to drive and difficult to maintain tracking bandwidth © Vishal Saxena -7- Fully-Differential Architecture • V doubled FS • 3-dB gain in SNR • Better CMRR • Noise immunity r • Input feedthrough e d o cancelled c n E • C nonlinearity in partially removed • Effect of V diff. cmi mitigated © Vishal Saxena -8- Flash ADC Design Considerations • Use a dedicated S/H (or T/H) for better dynamic performance – Can be avoided when using the A/D inside a ΔΣ loop • Large input range for the quantizer has several benefits – Increased step-size (V ) relaxes offset requirements on the comparators LSB – Reduced matching requirements result in small input cap to the S/H, easier to drive – Reduced input cap results in smaller clock routing parasitics – power savings in clock drivers • Comparator Design – See comparator design slides © Vishal Saxena -9- Flash ADC: Reference Ladder • Differential reference ladder • Decaps on the reference taps – large RC time-constant will not allow reference restoration after kickback noise – Small R will lead to power dissipation – Optimize RC • Subtract references from the input in a differential manner – Several topologies • Several architectures for the digital backend – May need to pipeline digital logic at high sampling rates >500 MS/s © Vishal Saxena -10-
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