Failure Analysis of Integrated Circuits: Tools and Techniques

255 Pages·1999·20.532 MB·English

by  Lawrence C. Wagner (auth.), Lawrence C. Wagner Ph.D. (eds.)

FAILURE ANALYSIS OF
INTEGRATED CIRCUITS
TOOLS AND TECHNIQUES
FAILURE ANALYSIS OF
INTEGRATED CIRCUITS
TOOLS AND TECHNIQUES
edited by
Lawrence C. Wagner, Ph.D.
Texas Instruments Incorporated
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication
Failure analysis of integrated circuits : tools and techniques / edited by
Lawrence C. Wagner.
p. cm. - (Kluwer international series in engineering and computer science ; SECS 494)
Includes bibliographical references and index.
ISBN 978-1-4613-7231-8 ISBN 978-1-4615-4919-2 (eBook)
DOI 10.1007/978-1-4615-4919-2
1. Semiconductors—Failures. 2. Integrated circuits—Testing.
3. Integrated circuits—Reliability. I. Wagner, Lawrence C. II. Series
TK7871.852.F35 1999
621,3815-dc21 98-51769
CIP
Copyright © 1999 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1999
Softcover reprint of the hardcover 1st edition 1999
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher, with the exception of
any material supplied specifically for the purpose of being entered and executed on a
computer system, for exclusive use by the purchaser of the work.
Printed on acid-free paper.
TABLE OF CONTENTS
Preface ............................................................................................ .
Acknowledgements ....................................................................... .
1 Introduction
Lawrence C. Wagner ................................................................ 1
1.1 Electrical Characterization 3
1.2 Die Exposure 3
1.3 Fail Site Isolation 4
1.4 Package Analysis 4
1.5 Physical and Chemical Analysis 4
1.6 Diagnostic Activities 5
1.7 Root Cause and Corrective Action 10
1.8 Conclusion 10
2 Electrical Characterization
Steven Frank, Wilson Tan and John F. West ........................ 13
2.1 Electrical Characterization 14
2.2 Curve Tracing 18
2.3 Electrical Characterization of State Dependent
Logic Failures 25
2.4 Memory Functional Failures 31
2.5 Challenges of Analog Circuit Fault Isolation and Analog
Building Blocks 34
2.6 Future Challenges for Circuit Characterization 39
3 Package Analysis: SAM and X-ray
Thomas M. Moore and Cheryl Hartfield ............................... 43
3.1 The Scanning Acoustic Microscope 44
3.2 The Real-Time X-Ray Inspection System 47
3.3 Application Examples 49
3.4 Summary and Trends in Nondestructive Inspection 54
4 Die Exposure
Phuc D. Ng o ............................................................................... 59
4.1 Didding Cavity Packages 59
4.2 Decapsulation of Plastic Packages 61
4.3 Alternative Decapsulation Methods 62
4.4 Backside Preparation for Characterization and Analysis 65
4.5 Future Requirements 66
5 Global Failure Site Isolation: Thermal Techniques
Daniel L. Barton ....................................................................... 67
5.1 Blackbody Radiation and Infrared Thermography 67
5.2 Liquid Crystals 70
5.3 Fluorescent Microthermal Imaging 76
5.4 Conclusion 84
6 Failure Site Isolation: Photon Emission Microscopy
OpticallElectron Beam Techniques
Edward I. Cole and Daniel L. Barton .................................... 87
6.1 Photon Emission Microscopy 88
6.2 Active Photon Probing 95
6.3 Active Electron Beam Probing 102
6.4 Future Developments for Photon and Electron Based
Failure Analysis 110
7 Probing Technology for IC Diagnosis
Christopher G. Talbot. ........................................................... 113
7.1 Probing Applications and Key Probing Technologies 113
vi
7.2 Mechanical Probing 114
7.3 E-beam Probing 117
7.4 Navigation and Stage Requirements 128
7.5 FIB for Probing and Prototype Repair 131
7.6 Backside Probing for Flip Chip IC 137
8 Deprocessing
Daniel yim. ..............................................................................1 45
8.1 IC Wafer Fabrication 145
8.2 Deprocessing Methods 148
8.3 New Challenges 156
9 Cross-section Analysis
Tim Haddock and Scott Boddicker ...................................... 159
9.1 Packaged Device Sectioning Techniques 159
9.2 Wafer Cleaving 162
9.3 Die Polishing Techniques 164
9.4 Cross Section Decoration: Staining 165
9.5 Focused Ion Beam (FIB) Techniques 166
9.6 Sectioning Techniques for TEM Imaging 168
9.7 Future Issues 173
10 Inspection Techniques
Lawrence C. Wagner ............................................................. 175
10.1 Microscopy 175
10.2 Optical Microscopy 177
10.3 Scanning Electron Microscopy 183
10.4 Focused Ion Beam Imaging 188
10.5 Transmission Electron Microscopy 189
10.6 Scanning Probe Microscopy 189
10.7 Future Considerations 192
vii
11 Chemical Analysis
Lawrence C. Wagner ............................................................. 195
11.1 Incident Radiation Sources 195
11.2 Radiation-Sample Interaction 197
11.3 Radiation Flux 197
11.4 Detectors 198
1 1.5 Common Analysis Techniques 198
11.6 Microspot FfIR 199
11.7 Other Techniques 201
11.8 Conclusion 203
12 Energy Dispersive Spectroscopy
Phuc D. Ngo ............................................................................. 205
12.1 Characteristic X-Ray Process and Detection 205
12.2 Quantitative Analysis 209
12.3 Sample Considerations 210
12.4 EDS Applications 212
12.5 Future Considerations 214
13 Auger Electron Spectroscopy
Robert K. Lowry. .................................................................... 217
13.1 The Auger Electron Process 2 I 7
13.2 AES Instrumentation and Characteristics 219
13.3 AES Data Collection and Analysis 220
13.4 Specimen, Material, and AES Operational Concerns 221
13.5 AES in Failure Analysis 223
13.6 Conclusion 226
14 Secondary Ion Mass Spectrometry, SIMS
Keenan Evans ......................................................................... 229
14.1 Basic SIMS Theory and Instrumentation 230
14.2 Operational Modes, Artifacts, and Quanitification 233
viii
14.3 Magnetic Sector SIMS Applications 234
14.4 Quadrupole SIMS Applications 236
14.5 Time-of-Flight SIMS Applications 238
14.6 Future SIMS Issues 239
15 Failure Analysis Future Requirements
David P. Vallett ....................................................................... 241
15.1 Ie Technology Trends Driving Failure Analysis 242
15.2 Global Failure Site Isolation 243
15.3 Development in Probing 245
15.4 Deprocessing Difficulties 246
15.5 Defect Inspection - A Time vs. Resolution Tradeoff 246
15.6 Failure Analysis Alternatives 248
15.7 Beyond the Roadmap 249
Index .............................................................................................. 251
ix
PREFACE
This book is intended as guide for those diagnosing problems in integrated circuits.
The process of selecting the tools and techniques to apply to a specific problem can
be bewildering and inefficient. As shown throughout the book, there are a wide
variety of tools and techniques employed in the diagnosis or failure analysis of
semiconductors. It is not practical to attempt to apply all of them to any specific
failure. Some are mutually exclusive. For example, it is not practical to attempt to
perform TEM and deprocess the exact same device. Some techniques are targeted
as specific failure mechanisms. Hence, it is not practical to apply them unless there
is an indication that the particular failure mechanism is possible. Further, the cost
and effort to apply all of the available techniques make it impractical.
This book provides a basic understanding of how each technique works. It is,
however, not intended to provide mathematical detail. Rather, it provides the
qualitative understanding generally required in making intelligent tool choices. The
book discusses the shortcomings and limitations of each technique as well as their
strengths. Typical applications of the techniques are used to illustrate the strengths of
the techniques. The book is also not intended to provide recipes for executing those
techniques. Those recipes are very dependent on the semiconductor manufacturing
process and the specific tool manufacturer. The diversity of semiconductor processes
and tools make it impractical to attempt that in a single volume.
As well as understanding how and when to apply each technique, it is important
to understand how they fit together. It is all together too easy to become tied up in
attempting to make one technique work on a specific failure. The diagnosis is really
part of a much bigger continuous improvement process. That process and the
integration of the tools are presented in the first chapter.
The semiconductor industry is propelled by the rapid pace of technological
improvements. The trends towards more complex, faster, denser devices with
smaller features and more layers. None of these trends makes diagnosis of problems
easier. Thus the technology of failure analysis must strive to keep pace. The efforts
of failure analysis to keep pace are described in the final chapter.
Acknowledgements
I would like to thank all of the chapter authors who contributed so much of their
time and effort to making this book possible. I would also like to thank the people
who helped with chapter reading including Richard Clark of Intel, Dave Vallett of
IBM, Ken Butler, Hal Edwards, Walter Duncan, Gordon Pollack, Tim Haddock,
John West, John Gertas, and Monte Douglas from Texas Instruments.
I would to like to especially thank Randy Harris for his support in completing this
book.