Emerging Imperatives for Engineers John A. Young Hewlett-Packard Company, Palo Alto ...

156 Pages·2002·0.61 MB·English

DAC87, Page 1
Keynote Address: Emerging Imperatives for Engineers

John A. Young
Hewlett-Packard Company, Palo Alto, California

In today's global economy, technology spreads rapidly across national borders, shortening
product life-cycles and shifting the nature of a firm's competitive position.

These changes have created new challenges and new expectations for engineers and engineering
managers.

In his keynote address, John A. Young will discuss his views on today's changing engineering
environment and how the engineering community might respond.
DAC87, Pages 2-8
SSIM: A SOFTWARE LEVELIZED COMPILED-CODE SIMULATOR

Laung-Terng Wang, Nathan E. Hoover, Edwin H. Porter, John J. Zasio
Research & Development Department, AIDA Corporation, Santa Clara, CA 95054

ABSTRACT
This paper presents a new logic simulation technique that uses software levelized compiled-code
(LCC) for synchronous designs. Three approaches are proposed: C source code, target machine
code and interpreted code. The evaluation speed for the software LCC simulator (SSIM) is about
140,000 (gate) evaluations per second using C source code or target machine code, or 50,000
evaluations per second using interpreted code. It is about 40 to 100 times slower than the AIDA
hardware LCC simulator, but is about one order of magnitude faster than a traditional software
event simulator. For a 32-bit multiplier with gate activity more than 100%, experiments indicate
that SSIM runs about 250 to 1,000 times faster than the AIDA event simulator that evaluates
about 4,500 gates per second.
Index Terms -- Levelized compiled-code (LCC) simulation, Logic simulation, Synchronous
design.

REFERENCES
[Aida86] Aida Corp. Aida Design System, Vols. II and IV, Aida Corp., Santa Clara, California, 1986.
[Blank84] Blank, T. "A Survey of Hardware Accelerators Used in Computer-aided Design" IEEE Design & Test of
Computers, Vol. 1, No. 3, pp. 21-39, August 1984.
[Breuer76] Breuer, M.A., and A.D. Friedman Diagnosis and Reliable Design of Digital Systems, Computer Science
Press, Inc., Woodland Hills, CA, 1976.
[Chiang86] Chiang, M., and R. Palkovic "LCC Simulators Speed Development of Synchronous Hardware"
Computer Design, pp. 87-91, March 1, 1986.
[Denneau82] Denneau, M.M. "The Yorktown Simulation Engine" Proc. of the ACM/IEEE 19th Design Automation
Conf., pp. 55-59, June 1982.
[Ishiura85] Ishiura, N., H. Yasuura, T. Kawata, and S. Yajima "High-Speed Logic Simulation on a Vector
Processor" Digest of Papers, IEEE 1985 Int'l Conf. on Computer-Aided Design (ICCAD-85), pp. 119-121, Santa
Clara, CA, Nov. 18-21, 1985.
[Pfister82] Pfister, G.F. "The Yorktown Simulation Engine: Introduction" Proc. of the ACM/IEEE 19th Design
Automation Conf., pp. 51-54, June 1982.
[Smith86] Smith, R.J., II "Fundamentals of Parallel Simulation" Proc. of the ACM/IEEE 23th Design Automation
Conf., pp. 2-12, June 1986.
DAC87, Pages 9-16
Simulator for MOS Circuits

Randal E. Bryant, Derek Beatty, Karl Brace, Kyeongsoon Cho, Thomas Sheffler
Carnegie Mellon University

Abstract
The COSMOS simulator provides fast and accurate switch-level modeling of MOS digital
circuits. It attains high performance by preprocessing the transistor network into a functionally
equivalent Boolean representation. This description, produced by the symbolic analyzer
ANAMOS, captures all aspects of switch-level networks including bidirectional transistors,
stored charge, different signal strengths, and indeterminate (X) logic values. The LGCC program
translates the Boolean representation into a set of machine language evaluation procedures and
initialized data structures. These procedures and data structures are compiled along with code
implementing the simulation kernel and user interface to produce the simulation program. The
simulation program runs an order of magnitude faster than our previous simulator MOSSIM II.

References
[1] Z. Barzilai, et al "SLS--a Fast Switch Level Simulator for Verification and Fault Coverage Analysis" 23rd
Design Automation Conf., ACM, 1986, pp. 164-170.
[2] R.E. Bryant "A Switch-Level Model and Simulator for MOS Digital Systems" IEEE Trans. on Computers Vol.
C-33, No. 2 (February, 1984), pp. 160-177.
[3] R. E. Bryant "Algorithmic Aspects of Symbolic Switch Network Analysis" IEEE Trans. on Computer-Aided
Design of Integrated Circuits, accepted for publication, 1987.
[4] R. E. Bryant "Boolean Analysis of MOS Circuits" IEEE Trans. on Computer-Aided Design of Integrated
Circuits, accepted for publication, 1987.
[5] E. Cerny, and J. Gecsei "Simulation of MOS Circuits by Decision Diagrams" IEEE Trans. on Computer-Aided
Design of Integrated Circuits, Vol. CAD-4, No. 4 (October, 1985), pp. 685-693.
[6] G. Ditlow, W. Donath, and A. Ruehli "Logic Equations for MOSFET Circuits" International Symposium on
Circuits and Systems, IEEE, 1983, pp. 752-755.
[7] I.N. Hajj, and D. Saab "Symbolic Logic Simulation of MOS Circuits" International Symposium on Circuits and
Systems, IEEE, 1983, pp. 246-249.
[8] C.E. Shannon "A Symbolic Analysis of Relay and Switching Circuits" Trans. of the AIEE, Vol. 57 (1938), pp.
713-723.
[9] I. Spillinger, and G. M. Silberman "Improving the Performance of a Switch-Level Simulator" IEEE Trans. on
Computer-Aided Design of Integrated Circuits, Vol. CAD-5, No. 3 (July, 1986), pp. 685-693.
[10] R. E. Tarjan "Fast Algorithms for Solving Path Problems" J. ACM, Vol. 23, No. 3 (July, 1981), pp. 594-614.
[11] C. J. Terman Simulation Tools for Digital LSI Design, PhD Thesis, MIT Dept. Elec. Eng. and Comp. Sci.,
October, 1983.
DAC87, Pages 17-25
A FAST SIGNATURE SIMULATION TOOL FOR BUILT-IN SELF-TESTING
CIRCUITS

S B Tan1, K Totton2, K Baker1, P Varma1, R Porter1
1GEC Research Limited, Hirst Research Centre, East Lane, Wembley, Middlesex HA9 7PP,
United Kingdom
2British Telecom Research Laboratories, UK

ABSTRACT
This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST)
circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator
generator comprises a controlling program called the EXECUTIVE and translation software
called SIM-GEN. SIM-GEN accepts a Hardware Description Language (HDL) representation of
the circuit-under-test as its input and produces C code simulation modules comprising Boolean
relations that represent the structure of the circuit. These C code modules are then compiled and
linked together to form the basis of the compiled code simulator. Simulation is invoked by
executing the compiled C code description of the circuit. The simulation time is minimised by
the use of parallel simulation techniques in conjunction with efficient functional models and
novel mapping techniques for the LFSRs. Performances approaching 5 Million Gate Evaluations
Per Second (GEPS) have been achieved using the FSS.

REFERENCES
[1] The AIDA Design System, AIDA Corporation, 1986
[2] M. A. Breuer, and A. D. Friedman "Diagnosis and Reliable Design of Digital Systems" Pitman Publishing
Limited, London, 1976.
[3] A. J. Briers and K. A. E. Totton "Random Pattern Testability by Fast Fault Simulation" Proceedings of the IEEE
Int. Test Conf., Sept. 1986, pp274-281
[4] R. M. Croft and K. Baker "Global Testability Tools for CATTE" Proceedings of the IEE Colloquium on 'Design
for Testability' 11th November 1985, London, UK.
[5] S. Evanczuk "Mixed-Level Simulation Acceleration" VLSI Systems Design, Feb. 1987, pp 62-70
[6] J Fox, G Surace, P Thomas "A Self-testing 2 µm CMOS Chip Set for FFT Applications" IEEE Journal of Solid
State Circuits, Vol. SC-22, No. 1, February 1987, pp 15-19
[7] J. R. Grierson, et al. "The UK 50000 - Successful Collaborative Development of an Integrated Design System for
a 5000 gate CMOS Array with Built-In Test" Proceedings of the DAC, 1983, pp 629-636
[8] N. Ishira, H Yasuura and S. Yagima "Time First Evaluation Algorithm for High-Speed Logic" Proceedings of
the ICCAD, 1984, pp 197-199
[9] N. A. Jones and K. Baker "An Intelligent Knowledge-Based System Tool for High-Level BIST Design"
Proceedings of the IEEE Int. Test Conf., Sept. 1986, pp 743-749
[10] S. Koeppe and C. W. Starke. "Logiksimulation Komplexer Schaltungen Fuer sehr grose Testaengin" Vortraege
der NTG-Fachtagung, Baden-Baden, March 1985, pp 73-80
[11] H. E. Krohn " Vector Coding Techniques for High Speed Sigital Simulation" Proceedings of the 18th DAC
1981, pp 525-529
[12] W. W. Peterson "Error Correcting Codes" John Wiley, 1961
[13] S. Shaw "The Alvey Approach to Self-Testing" Silicon Design, June 1986, pp 16-17
[14] TTL Data Book, Texas Instruments, 1971.
[15] T. W. Williams and K. P. Parker "Design for Testability - A Survey" Proceedings of the IEEE, January 1983,
pp 98-112
DAC87, Pages 26-34
AN IMPROVED SYSTEMATIC METHOD FOR CONSTRUCTING SYSTOLIC
ARRAYS FROM ALGORITHMS

Nikrouz Faroughi, Michael A. Shanblatt
Department of Electrical Engineering, Michigan State University, East Lansing, Michigan 48824

An improved systematic method is introduced which reduces the number of ad hoc steps and
provides all possible systolic solutions for a given algorithm. Algorithms are modeled using
index space (geometric) representations where the index transformation matrices are determined
systematically. Systolic arrays are produced by geometric projections.

References
[1] H. T. Kung "Why Systolic Architectures?" Computer Magazine Vol. 15, No. 2, 1982, pp 37-46.
[2] J. L. Bentley and H. T. Kung "An Introduction to Systolic Algorithm and Architectures" Nav. Res. Rev. (USA),
Vol. 35, No. 2, 1983, pp 3-16.
[3] J. A. B. Fortes, K. S. Fu and B. W. Wah "Systematic Approaches to the Design of Algorithmically Specified
Systolic Arrays" 1985 Int'l Conf. on Acoustics, Speech, and Signal processing, Tampa, Florida, Mar. 1985, pp 300-
303.
[4] J. A. B. Fortes and D. I. Moldovan "Parallelism Detection and Transformation Techniques Useful for VLSI
Algorithms" J. of Parallel and Distributed Computing, 1985, pp 277-301.
[5] O. H. Ibarra, S. M. Kim, and M. A. Palis "Designing Systolic Algorithms using Sequential Machines" IEEE
Trans. on Computers, Vol. C-35, No. 6, June 1986, pp 531-542.
[6] D. I. Moldovan "On the Design of Algorithms for VLSI Systolic Arrays" Proceedings of the IEEE, Vol. 71, No.
1, Jan. 1983, pp 113-120.
[7] D. D. Gajski and R. H. Kuhn "Guest Editors' Introduction New VLSI Tools" IEEE Computer, No. 12, Dec.
1983, pp 11-14.
[8] P. R. Cappello and K. Steiglitz "Unifying VLSI Array Designs with Geometric Transformations" Conf. on
Parallel Processing, 1983, pp 448-457.
[9] R. H. Kuhn "Transforming Algorithms for Single-Stage and VLSI Architectures" Workshop on Interconnection
Networks for Parallel and Distributed Processing, 1980, pp 11-19.
[10] N. Faroughi "A New Method for Systematic Construction of Systolic Arrays" Ph.D. Dissertation, Dept. of
Electrical Engineering, Michigan State University, 1987, Unpublished.
[11] C. Mead and L. Conway "Introduction to VLSI Systems" Addison-Wesley, Section 8.3, 1980.
[12] Kai Hwang and Yen-Keng Cheng "VLSI Computing Structures for Solving Large-Scale Linear System of
Equations" Conf. on Parallel Processing, 1980, pp 217-227.
DAC87, Pages 35-41
PREDICTING AREA-TIME TRADEOFFS FOR PIPELINED DESIGN

Rajiv Jain, Alice Parker
Department of Electrical Engineering – Systems, University of Southern California, Los Angeles
CA 90089-0781

Nohbyung Park
Department of Electrical Engineering, University of California Irvine, CA 92717

ABSTRACT
In this paper we give a model for predicting the shape of cost-speed tradeoff curves for pipelined
designs. The model includes prediction of the number of operators, registers and multiplexers
from a behavioral specification. It has been verified with the designs generated by an automated
pipeline synthesis program, Sehwa. This model was developed as a part of the ADAM Advanced
Design Automation System of the University of Southern California.

REFERENCES
[1] S. Y. Kung "On Supercomputing with Systolic/Wavefron Array Processors" Proc. IEEE, Vol. 72, No.7, July
1984.
[2] F. J. Kurdahi and A. Parker "PLEST: A program for Area Estimation of VLSI Integrated Circuits" Proc. 23rd
Design Automation Conference, ACM SIGDA, IEEE Computer Society, June 1986.
[3] N. Park and A. Parker "SEHWA: A program for Synthesis of Pipelines" Proc. 23rd Design Automation
Conference, ACM SIGDA, IEEE Computer Society, June 1986.
[4] J. Granacki, D. Knapp and A. Parker "The ADAM Advanced Design Automation System: Overview, Planner
and Natural Language Interface" Proc. 22nd Design Automation Conference, ACM SIGDA, IEEE Computer
Society, June 1985.
DAC87, Pages 42-49
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis

Ramesh Harjani, Rob. A. Rutenbar, L. Richard Carley
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh,
Pennsylvania 15213

Abstract
An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit
topologies are represented as a hierarchy of functional blocks; a planning mechanism is
introduced to translate performance specifications between levels in this circuit hierarchy. A
prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS
operational amplifiers from performance specifications and process parameters, and
demonstrates the workability of the approach.

References
[1] P. E. Allen and E. R. Macaluso "AIDE2: An Automated Analog IC Design System" Proc. IEEE Custom
Integrated Circuiuts Conf., 1985.
[2] P. E. Allen and P. R. Barton "A Silicon Compiler for Successive Approximation A/D and D/A Converters" Proc.
IEEE Custom Integrated Circuiuts Conf., 1986.
[3] M. R. Barbacci "Instruction Set Specifications (ISPS): The Notation and its Applications" IEEE Trans.
Computers, C20(1), January 1981.
[4] W. P. Birmingham and D. P. Siewiorek "MICON: A Knowledge Based Single Board Computer Designer" Proc.
21st ACM/IEEE Design Automation Conf., 1984.
[5] R. J. Bowman and D. J. Lane "A Knowledge-Based System for Analog Integrated Circuit Design" Proc. IEEE
Internat. Conf. on Computer-Aided Design, 1985.
[6] F. D. Brewer and D. Gajski "An Expert-System Paradigm for Design" Proc. 23rd ACM/IEEE Design
Automation Conf., 1986.
[7] M. Bushnell and S. Director "VLSI CAD Tool Integration using the ULYSSES Environment" Proc. 23rd
ACM/IEEE Design Automation Conf., 1986.
[8] R. Castello and P. R. Gray "Performance Limitations in Switched-Capacitor Filters" IEEE Trans. on Circuits and
Systems, CAS-32(9), September 1985.
[9] J. De Kleer and G. J. Sussman "Propagation of Constraints Applied to Circuit Synthesis" Circuit Theory and
Applications, 8, 1980.
[10] M. G. R. Degrauwe and W. M. C. Sansen "The Current Efficiency of MOS Transconductance Amplifiers"
IEEE Journal of Solid-State Circuits, SC-19(3), June 1984.
[11] C.D. Kimble, A.E. Dunlop, G.F. Gross, V.L. Hein, M.Y. Luong, K.J. Stern, E.J. Swanson "Autorouted Analog
VLSI" Proc. Custom Integrated Circuit Conference, 1985.
[12] F. M. El-Turky and R. A. Nordin "BLADES: An Expert System for Analog Circuit Design" Proc. IEEE Intl.
Symp. Circuits and Systems 1986.
[13] M. W. Hauser and R. W. Brodersen "Circuit and Technology Considerations for MOS Delta-Sigma A/D
Converters" IEEE Intl. Symp. on Circuits and Systems, May 1986.
[14] W.J. Helms and K.C. Russel "Switched Capacitor Filter Compiler" Proc. Custom Integrated Circuit
Conference, 1986.
[15] J. Kim, J. McDermott and D. P. Siewiorek "Exploiting Domain Knowledge in IC Cell Layout" IEEE Design
and Test, 1(3)1984.
[16] T. J. Kowalski and D. E. Thomas "The VLSI Design Automation Assitant: What's in a Knowledge Base" Proc.
22nd ACM/IEEE Design Automation Conf., 1985.
[17] B. Nye, A. Sangiovanni-Vincentelli, J. Spoto and A. Tits, "DELIGHT SPICE: An Optimization-Based System
for the Design of Integrated Circuits" Proc. Custom Integrated Circuit Conference, 1983.
[18] T. W. Pickerrell "New Analog Capabilities on Semi-Custom CMOS" Proc. Custom Integrated Circuit
Conference, 1983.
[19] T. Pletersek et al "Analog LSI Design with CMOS Standard Cells" Proc. IEEE Custom Integrated Circuit
Conference, 1985.
[20] A. Ressler A Circuit Grammer for Operational Amplifier Design, PhD dissertation, Artificial Intelligence
Laboratory, Massachusetts Institute of Technology, 1984.
[21] G. L. Roylance "A Simple Model of Circuit Design" Master's thesis, Massachusetts Institute of Technology,
1980.
[22] G. I. Serhan "Automated Design of Analog LSI" Proc. IEEE Custom Integrated Circuit Conference, 1985.
[23] G. J. Sussman and R. M. Stallman "Heuristic Techniques in Computer-Aided Circuit Analysis" IEEE
Transactions on Circuits and Systems, CAS-22(11), November 1975.
[24] D. Thomas "The Automatic Synthesis of Digital Systems" Proc. IEEE, 69(10), October 1981.
[25] D. Thomas, et al "Automatic Data Path Synthesis" IEEE Computer, 16(12), December 1983.
[26] R. Widlar and M. Yamatake "A 150W Opamp" Digest of Tech. Papers, Intl. Solid State Circuits Conf.,
February 1985.
[27] B. C. Williams "Qualitative Analysis of MOS Circuits" Master's thesis, Massachusetts Institute of Technology,
1984.
DAC87, Pages 50-55
AN AUTOMATIC RECTILINEAR PARTITIONING PROCEDURE FOR STANDARD
CELLS

Mely Chen Chi
AT&T Bell Laboratories, Murray Hill, NJ 07974

ABSTRACT
This paper describes a new approach to automatically partition and place the standard cells in a
rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O
pads. The macro cells may be placed anywhere on the chip. The topological and physical
constraints, and the net list connectivity are accounted for simultaneously. This procedure has
been implemented in the AT&T Bell Laboratories LTX2 chip layout system.

REFERENCES
[1] A. E. Dunlop and B. W. Kernighan "A procedure for Layout of Standard-Cell VLSI circuits, IEEE Transactions
on Computer-aided Design, pp. 92-98 January 1985.
[2] M. Hild, and J. O. Piednoir "Efficient placement Algorithms for VLSI" VLSI Design, pp. 46-50, April 1985.
[3] H. Terai et al. "Performance Analysis of Automatic placement and Routing for Large-Scale CMOS Master
slices" Proc. of the IEEE International Conference on Computer Design, pp. 536-539, 1983.
[4] R. Putatunda et al. "An optimized and Unique Placement Approach for Very Large Semicustom IC Designs:
VLSI in Computers" Proc. of the IEEE International Conference on Computer Design, pp. 440-444, 1985.
[5] B. W. Colbry and J. Soukup "Layout Aspects of the VLSI Microprocessor Design" Proc. of the IEEE
International Symposium on Circuits and Systems, pp. 1214-1228, may 1982
[6] A. E. Dunlop "Automatic Layout of Gate Arrays" Proc. of the IEEE Symposium on Circuits and Systems, pp.
1245-1248, 1983.
[7] B. W. Kernighan and S. Lin "An efficient heuristic procedure for partitioning graphs" Bell sys. tech. J. Vol. 49, p
291-308, February 1970.
[8] A. E. Dunlop and V. D. Agrawal et al. "Chip Layout Optimization Using Critical Path Weighting" Proc. of the
IEEE 21st Design Automation Conference, pp. 133-136, 1984.
DAC87, Pages 56-59
STANDARD CELL PLACEMENT USING SIMULATED SINTERING

Lov K. Grover
AT&T Bell Laboratories, Murray Hill, New Jersey 07974

ABSTRACT
Simulated annealing is a powerful optimization technique based on the annealing phenomenon in
crystallization. In this paper we propose a simulated sintering technique which is analogous to
the sintering process in material processing. In sintering one improves the quality of a processed
material by heating it to a temperature close to the melting point. Analogously, we show that by
starting out with a good initial configuration instead of a random configuration, and restricting
uphill moves, we can considerably speed up simulated annealing. We use this idea for a standard
cell placement program - GRIM in LTX2, an AT&T Bell Labs VLSI layout system. The initial
configuration is produced either by changes to a layout the designer had done previously, or else
by a fast program like min-cut. We obtain improvements of about 10% in chip area starting from
a min-cut placement, in times about 3 times faster than our simulated annealing program (which
itself is several times faster than other well known simulated annealing programs).

REFERENCES
[1] Garey & Johnson "Computers & Intractability, A guide to the theory of NP Completeness" Freeman, 1979.
[2] S. Kirkpatrick, et al. "Optimization by simulated annealing" Science, vol. 220, pp. 671-680, 1983.
[3] N. Metropolis et al. J. Chem. Phys. Vol. 21, pp. 1087, 1953. For a recent review see K. Binder, editor, "The
Monte Carlo method in Statistical Physics," New York: Springer Verlag, 1978.
[4] B.W. Colbry & J. Soukup "Layout aspects of the VLSI Microprocessor Design" International Symposium on
Circuits and Systems, May 1982, pp. 1214-1228.
[5] A. E. Dunlop "Automatic Layout of Gate Arrays" International Symposium on Circuits and Systems, May 1983,
pp. 1245-1248.
[6] A. E. Dunlop & B. W. Kernighan "A Placement procedure for Polycell VLSI Circuits" Proceedings of the
ICCAD, pp. 1045-1048, 1983.
[7] Lov K. Grover "A new simulated annealing algorithm for standard cell placement" Proceedings of the ICCAD,
1986.
[8] Lov K. Grover "GRIM - A Fast Simulated Annealing Program for Standard Cell Placement" Proceedings of the
CICC, 1987.
[9] Steve White "Concepts of scale in simulated annealing" Proceedings of the ICCD, 1984.
[10] Lov K. Grover "Simulated Annealing using approximate calculations" submitted to IEEE Transactions on
CAD.