Manho Lee · Jun So Pak Joungho Kim Editors Electrical Design of Through Silicon Via Electrical Design of Through Silicon Via Manho Lee Jun So Pak • • Joungho Kim Editors Electrical Design of Through Silicon Via 123 Editors Manho Lee Jun SoPak JounghoKim System LSI Department of ElectricalEngineering Samsung ElectronicsCo.,Ltd KAIST Hwaseong,Gyeunggi Daejeon Republic ofKorea Republic ofKorea ISBN 978-94-017-9037-6 ISBN 978-94-017-9038-3 (eBook) DOI 10.1007/978-94-017-9038-3 Springer Dordrecht Heidelberg New YorkLondon LibraryofCongressControlNumber:2014936740 (cid:2)SpringerScience+BusinessMediaDordrecht2014 Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpartof the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation,broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionor informationstorageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilar methodology now known or hereafter developed. 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Printedonacid-freepaper SpringerispartofSpringerScience+BusinessMedia(www.springer.com) To my beloved wife, Jeangeun Byun, and my lovely daughter, Justine Kim, who are the center of my universe, for their never-ending love, support, and understanding —Joungho Kim Contents 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Jun So Pak and Joungho Kim 2 Electrical Modeling of a Through Silicon Via . . . . . . . . . . . . . . . 23 Joohee Kim, Jun So Pak and Joungho Kim 3 High-Speed TSV-Based Channel Modeling and Design . . . . . . . . 61 Heegon Kim, Jun So Pak and Joungho Kim 4 Noise Coupling and Shielding in 3D ICs . . . . . . . . . . . . . . . . . . . 115 Jonghyun Cho, Jun So Pak and Joungho Kim 5 Thermal Effects on TSV Signal Integrity. . . . . . . . . . . . . . . . . . . 147 Manho Lee, Jun So Pak and Joungho Kim 6 Power Distribution Network Modeling and Analysis for TSV and Interposer-Based 3D-ICs in the Frequency Domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Kiyeong Kim, Jun So Pak and Joungho Kim 7 TSV Decoupling Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Eunseok Song, Jun So Pak and Joungho Kim About the Authors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 vii Contributors JonghyunCho DepartmentofElectricalEngineering,KAIST,Daejeon,Republic of Korea Heegon Kim Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea Joohee Kim Rambus INC., San Jose, California, USA JounghoKim Department ofElectricalEngineering, KAIST,Daejeon,Republic of Korea Kiyeong Kim Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea ManhoLee DepartmentofElectricalEngineering,KAIST,Daejeon,Republicof Korea Jun So Pak System LSI, Samsung Electronics Co., Ltd., Hwaseong, Gyeunggi, Republic of Korea EunseokSong DepartmentofElectricalEngineering,KAIST,Daejeon,Republic of Korea, e-mail: [email protected] ix Chapter 1 Introduction Jun So Pak and Joungho Kim Abstract TSV (Through Silicon Via) is now a key-technology in the mobile era because it can enable high-performance, hybrid, light-weight, small mobile devices with longer battery lifetimes and low manufacturing costs by reusing IP (intellectual property) and selecting optimized and high-yield, functional chips. ThischapterdiscusseswhyTSV-based3DICs(3dimensionalintegratedcircuits) areapossiblesolutionforfuturemobiledevicesfromtheperspectiveofexploiting advantages in their electrical designs. This chapter also provides a brief intro- duction to the electrical analysis of TSVs based on MIS (Metal-Insulator-Semi- conductor) analyses. Keywords Differential signal TSV (cid:2) Equivalent circuit model (cid:2) Single-ended signal TSV (cid:2) Scalable model (cid:2) TSV channel (cid:2) 3D IC 1.1 TSV-Based 3D ICs Employing high-performance, hybrid systems with small form factors and short design cycles has become the most important IC design approach for worldwide mobile devices. There are two approaches to satisfy the requirements of this approach. The first includes shrinking the transistor size (device scaling to con- tinuetomeetMoore’slaw),developingICshrinkagetechnologies,andassembling J.Kim DepartmentofElectricalEngineering,KAIST,Daejeon,RepublicofKorea e-mail:[email protected] J.S.Pak(&) SystemLSI,SamsungElectronicsCo.,Ltd.,Hwaseong,Gyeunggi,RepublicofKorea e-mail:[email protected] M.Leeetal.(eds.),ElectricalDesignofThroughSiliconVia, 1 DOI:10.1007/978-94-017-9038-3_1, (cid:2)SpringerScience+BusinessMediaDordrecht2014 2 J.S.PakandJ.Kim Fig.1.1 System-in-packageversussystem-on-chip Fig.1.2 ADVDplayerasanexampleofahigh-performancesysteminasmallformfactor ICs on a shrunken single chip, namely, the One Chip Solution (SoC, system- on-chip). The second approach includes securing KGDs (known good dies) to meet system functions and developing high-performance technologies for the interconnections betweenchips,namely,theMulti-ChipSolution(SiP,system-in- package), as shown in Fig. 1.1. For example, in Fig. 1.2, a conventional DVD player has four main functional blocks or chips, such as a DRAM, an MPEG, an 1 Introduction 3 MPU,andaDSP.TomaketheDVDplayersmaller,lighter,andportable,itshould haveasmallercaseandasmallermainboardembeddedinthecase.Ofcourse,the main board must work better than the previous design. This requirement can be accomplished mainly by reducing the interconnection lengths between the blocks or chips with physical dimension matching, a capability that is easily understood by those who have seen any main board of any electric system and noted that the area occupied by the interconnections is much larger than that of the main func- tional blocks or chips and that the best way to reduce the physical size of the system is to control the area of the interconnections. However, because the interconnectionsarenecessaryfortheoperationoftheDVDplayer,thenumberof interconnectionsonthemainboardcannotbereduced.Therefore,theSoCandSiP technologies, including the TSV-based 3D IC technology, were introduced to dramatically reduce the interconnection area. As shown in Fig. 1.2, the SoC and SiPapproachescanachieveveryshortandnarrowinterconnectionsinaverysmall area. They also enable systems with high performance by inducing only small electricalparasiticlosses attheinterconnections.Theparasiticelectricalelements of interconnections are well known cause large signal distortion, long waiting times, and large interference. In fact, during the past decade, SoC and SiP approaches have been competing witheachother,andtheiradvantageshavebeenaddressed[1–3].SoChasseveral merits, such as high-speed and wide-bandwidth interconnections between func- tionalblocksonasinglechipandasmallpackagesize.Meanwhile,SiPachievesa lowdevelopmentcostbyadoptingKGDsandpassivecomponents,highflexibility regarding combined system functions, easy power management, small digital-to- analog coupling, and a short time to market. Of course, those two advantage groupshavebecomeweakpointstoeachother.InTable 1.1,theprosandconsof SiP and SoC are listed and compared in detail. At first glance, SiP is more attractive than SoC because the pros of SiP are more numerous. However, the conventional SiP approach based on bond-wire technology has several critical weakpointsarisingoutoftheinherentlonglengthofthebondwiresandbond-pad locations within the very limited area of the chip periphery. The long length and consequent large inductance of the wires and the limited number of bond-pads cause a narrow signal bandwidth and result in a low system speed. Additionally, thehookshapeofthebondwiresandtherelativelylargearearequiredforchip-to- chip interconnections increase the package size in the vertical and horizontal directions. To overcome the cons of conventional SiP technology, TSV-based 3D IC has been adopted by SiP technology as shown in Figs. 1.2 and 1.3. TSV is an abbreviation for ‘‘through silicon via,’’ which is a metal pillar inside the silicon (Si) wafer with a silicon oxide coating (‘liner’) to block the DC leakage current betweenthemetalpillarandthesiliconwafer.ThedetailedstructureofTSVswill beaddressedinFig. 1.12oftheSect.1.2.AsmentionedinFig. 1.3,TSV-based3D IC technology has many interesting motivations. First, it increases the functional densityinalimitedarea,forexample,byallowingforaverysmallpackageanda very small system for current mobile applications without performance