EFFICIENT BRANCH AND BOUND SEARCH WITH APPLICATION TO COMPUTER-AIDED DESIGN FRONTIERS IN ELECTRONIC TESTING Consulting Editor Vishwani D. Agrawal Books in the series: IDDQ Testing of VLSI Circuits, R. Gulati, C. Hawkins ISBN: 0-7923-9315-5 Economics of Electronic Design, Manufacture and Test, M. Abadir, A.P. Ambler ISBN: 0-7923-9471-2 Testability Concepts for Digital ICs: The Macro Test Approach F.P.M. Beenker, R.G. Bennetts, A.P. Thijssen ISBN: 0-7923-9658-8 EFFICIENT BRANCH AND BOUND SEARCH WITH APPLICATION TO COMPUTER-AIDED DESIGN by Xinghao Chen Rutgers University and Michael L. Bushnell Rutgers University ~. " KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht / London Distributors for North America: Kluwer Academic Publishers 101 Philip Drive Assinippi Park Norwell, Massachusetts 02061 USA Distributors for all other countries: Kluwer Academic Publishers Group Distribution Centre Post Office Box 322 3300 AH Dordrecht, THE NETHERLANDS Library of Congress Cataloging-in-Publication Data A C.I.P. Catalogue record for this book is available from the Library of Congress. ISBN-13: 978-1-4612-8571-7 e-ISBN-13: 978-1-4613-1329-8 DOl: 10.1007/978-1-4613-1329-8 Copyright © 1996 by Kluwer Academic Publishers Softcover reprint of the hardcover 1s t edition 1996 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, mechanical, photo-copying, recording, or otherwise, without the prior written permission of the publisher, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061 Printed on acid-free paper. To Christine Yi-Feng Chen Megan Elizabeth and Amy Katherine Bushnell CONTENTS FOREWORD xi PREFACE xiii Part I THEORY 1 1 INTRODUCTION 3 1.1 Branch-and-Bound Search 3 1.2 Efficient Branch-and-Bound Search 6 1.3 Justification with Branch-and-Bound 7 1.4 Why Use Justification Equivalence? 7 1.5 Prior Work 8 1.6 Organization of the Book 8 2 JUSTIFICATION EQUIVALENCE 11 2.1 Introduction 11 2.2 Justification Decomposition 13 2.3 Properties 15 2.4 Identification of Shared Justification Decisions 17 2.5 Justification Equivalence 17 2.6 Efficient Representation 19 2.7 An ATPG Example 21 2.8 Summary 23 3 JUSTIFICATION IN FINITE STATE SPACE 25 3.1 Introduction 25 3.2 What is State Justification? 26 viii 3.3 Justifiability of States 28 3.4 State Justification Equivalence 31 3.5 Covering Properties 32 3.6 An Example 33 3.7 Summary 34 Part II APPLICATIONS 35 4 SEQUENTIAL CIRCUIT TEST GENERATION 37 4.1 Introduction 37 4.2 What is Sequential Circuit Test Generation? 38 4.3 Complexity of Test Generation 41 4.4 How Can Justification Equivalence Help? 42 4.5 Prior Work 44 5 FAULT EFFECTS 55 5.1 Introduction 55 5.2 Fault Effect Analysis 55 5.3 Summary 57 6 THE SEST ALGORITHM 59 6.1 Introduction 59 6.2 The Control Flow 62 6.3 Complexity of Retrieval 64 6.4 Implementation 67 6.5 Summary 73 7 EXPERIMENTAL RESULTS 75 7.1 Introduction 75 7.2 Experimental Procedures 76 7.3 ATPG Time Proportions 76 7.4 SEST Efficiency Evaluation 78 7.5 Benchmark Results 88 7.6 Summary 94 Contents ix 8 REDUNDANCY IDENTIFICATION 97 8.1 Introduction 97 8.2 Why is Redundancy Identification Needed? 98 8.3 Prior Work 98 8.4 Efficient Redundancy Identification 99 8.5 Summary 101 9 LOGIC VERIFICATION 103 9.1 Introduction 103 9.2 Prior Work 105 9.3 Logic Verification via Test Generation 107 9.4 Summary 108 10 CONCLUSION 109 A SEST USER'S GUIDE 111 A.1 INTRODUCTION 111 A.2 COMMAND SYNOPSIS 112 A.3 Options 112 A.4 INPUTS and OUTPUTS 112 A.5 Output Files 117 A.6 Example 117 A.7 Down-Loading SEST from the Disk 122 A.8 Reporting Bugs 123 A.9 Author 123 REFERENCES 125 INDEX 143 FOREWORD What do languages, alphabets, a printing press, books, a copying machine and a computer have in common? They all make storage and retrieval of information possible. History tells us that the rate of progress accelerates with the increase in the information handling capability. Obviously, we can advance farther if we can build upon the previous knowledge rather than reinventing everything from scratch. According to Robert Tarjan," Actually, computers do much better at speed chess than at slow chess. If you give both the human and the computer more time, the human will slaughter the computer. If you speed up things sufficiently then anybody, even Kasparov, will lose to a computer." (C.W. Gear, Editor, Computation & Cognition, Philadelphia: SIAM, 1991.) Indeed, using intelli gence or intuition, a human chess player quickly rejects fruitless moves. The computer, lacking any intuition, recomputes all details even if the same, or a similar, situation arises. When we speed up the game, it is the raw speed, and not the intelligence, of the computer which allows it to win. Suppose we define intuition as the ability to recognize similarity among things that are not completely identical. Given that a computer can memorize, can we add intuition? There is a class of problems, mostly involving optimization or search, that is frequently encountered in engineering practice. The complexity of these prob lems is so great that even fast computers run into difficulty. The authors, Chen and Bushnell, have conducted significant research on speeding up computer solutions of this type of problems. Their idea is to save the computed infor mation for reuse in the future. As the search for a solution progresses, the amount of information and, hence, the burden of storing it grows. The over head of information storage and retrieval must be weighed against the cost of the repeated calculations that could be avoided. The authors determined that the most useful information is that about sub-spaces containing no solution. However, the ingenuity of their method lies in procedures through which they can recognize cases that are only similar to, but are not exactly the same as, xii the previously stored cases. The concepts presented in this book are general and are applicable to a variety of problems. The book is particularly useful to readers interested in testing of digital cir cuits. Those who work in that area are familiar with severe limitations of test generation programs, especially when dealing with sequential circuits. Most programs make good progress in the beginning, but slow down toward the end when left with hard-to-detect faults. A reader will find it interesting to exper iment with the authors' SEST program, supplied with this book. It may run slightly slower in the beginning due to the time used in storing the learned in formation. However, as test generation progresses, the program picks up speed and completes much earlier than most other programs. The topic of this book is important but has been largely neglected in the liter ature. I expect that it will be received with the same enthusiasm as the three previous volumes in the Frontiers in Electronic Testing Series. Vishwani D. Agrawal Consulting Editor Frontiers in Electronic Testing Series AT&T Bell Laboratories [email protected]