Dual Channel 11 Bit, 200 MSPS ADC with SNRBoost datasheet

68 Pages·2017·3.39 MB·English

ADS62C17
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Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost
FEATURES • ProgrammableGainupto6dBforSNR/SFDR
1
• MaximumSampleRate:200MSPS Trade-off
• 11-bitResolutionwithNoMissing Codes • DCOffsetCorrection
• 90dBcSFDRatFin=10MHz • GainTuningCapabilityinFineSteps(0.001
• 79.8dBFSSNR at125MHzIF,20MHzBW dB) AllowsChannel-to-channel GainMatching
usingTIproprietarySNRBoosttechnology • SupportsInputClockAmplitudeDownto400
• TotalPower 1.1Wat200MSPS mVp-pDifferential
• 90dBCross-talk • InternalandExternal ReferenceSupport
• DoubleDataRate(DDR)LVDSandParallel • 64-QFNPackage(9mm×9mm)
CMOSOutputOptions
DESCRIPTION
ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low
power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width
communicationsapplications.
ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to
quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital
functionssuchasADC offsetcorrection,gain(0 to6dB instepsof0.5 dB)andgain tuning(infine steps of 0.001
dB).
The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain
tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching.
Thedevicealsoincludesadcoffsetcorrectionloopthat canbeusedto canceltheADCoffset.
Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes
internal references while the traditional reference pins and associated decoupling capacitors have been
eliminated.Nevertheless,thedevicecanalsobedrivenwith anexternalreference.
Thedeviceisspecifiedovertheindustrialtemperaturerange(–40°Cto85°C).
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS62C17
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Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam
duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates.
D D
AVDD AGND DRVD DRGN
LVDS
INTERFACE
DA0P/M
Digital
Processing DA2P/M
Block DA4P/M
IINNAA__MP SHa&moldple 1A4DbCit SNRBoost 11bit DSeDrRializer DA6P/M
DA8P/M
ChannelA
DA10P/M
CLKP OUTPUT
CLOCKGEN CLOCK CLKOUTP/M
CLKM
BUFFER
DB0P/M
Digital
Processing DB2P/M
INB_P Sample 14bit Block DB4P/M
INB_M H&old ADC SNRBoost 11bit DSeDrRializer DB6P/M
DB8P/M
ChannelB
DB10P/M
CONTROL
VCM REFERENCE INTERFACE
ADS62C17 SDOUT
CTRL1CTRL2CTRL3 RESETSCLKSENSDATA
Figure1. ADS62C17BlockDiagram
PACKAGE/ORDERING INFORMATION
TRANSPORT
PACKAGE- PACKAGE SPECIFIED
PRODUCT PACKAGEMARKING ORDERINGNUMBER MEDIA,
LEAD DESIGNATOR TEMPERATURERANGE
QUANTITY
ADS62C17IRGCR
ADS62C17 QFN-64 RGC –40°Cto85°C AZ62C17 TapeandReel
ADS62C17IRGCT
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THERMAL CHARACTERISTICS(1)
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
PARAMETER TESTCONDITIONS TYP UNIT
Rq JA(2) Solderedthermalpad,noairflow 22
Solderedthermalpad,200LFM 15 °C/W
Rq JT(3) Bottomofpackage(thermalpad) 0.57
(1) WithaJEDECstandardhighKboardand5x5viaarray.SeeExposedPadintheApplicationInformation.
(2) Rq JAisthethermalresistancefromthejunctiontoambient.
(3) Rq JTisthethermalresistancefromthejunctiontothethermalpads.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
SupplyvoltagerangeAVDD -0.3to3.9
V
SupplyvoltagerangeDRVDD –0.3to2.2
VoltagebetweenAGNDandDRGND –0.3to0.3
VoltagebetweenAVDDtoDRVDD(whenAVDDleadsDRVDD) 0to3.3 V
VoltagebetweenDRVDDtoAVDD(whenDRVDDleadsAVDD) –1.5to1.8
Voltageappliedtoexternalpin,VCM(inexternalrefersncemode) –0.3to2.0
–0.3Vtominimum
Voltageappliedtoanaloginputpins–INP_A,INM_A,INP_B,INM_B
(3.6,AVDD+0.3V) V
Voltageappliedtoinputpins–CLKP,CLKM(2),RESET,SCLK,SDATA,SEN,CTRL1,
–0.3VtoADD+0.3V
CTRL2,CTRL3
T Operatingfree-airtemperaturerange –40to85 °C
A
T Operatingjunctiontemperaturerange 125 °C
J
T Storagetemperaturerange –54to150 °C
stg
ESD,humanbodymodel 2 kV
(1) Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder“recommendedoperating
conditions”isnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability.
(2) WhenAVDDisturnedoff,itisrecommendedtoswitchofftheinputclock(orensurethevoltageonCLKP,CLKMis<|0.3V|.This
preventstheESDprotectiondiodesattheclockinputpinsfromturningon.
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RECOMMENDED OPERATING CONDITIONS(1)
MIN TYP MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 3.15 3.3 3.8 V
DRVDD Digitalsupplyvoltage 1.7 1.8 1.9 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
PP
Inputcommon-modevoltage 1.5±0.1 V
VoltageappliedonCMinexternalreferencemode 1.5±0.05 V
Maximumanaloginputfrequencywith2Vppinputamplitude (1) 500 MHz
Maximumanaloginputfrequencywith1Vppinputamplitude (1) 800 MHz
CLOCKINPUT
Inputclocksamplerate 1 200 MSPS
InputClockamplitudedifferential(V –V )
CLKP CLKM
Sinewave,ac-coupled 0.2 3.0 V
PP
LVPECL,ac-coupled 1.6 V
PP
LVDS,ac-coupled 0.7 V
PP
LVCMOS,single-ended,ac-coupled 3.3 V
Inputclockdutycycle 40% 50% 60%
DIGITALOUTPUTS
C MaximumexternalloadcapacitancefromeachoutputpintoDRGND 5 pF
L
R DifferentialexternalloadresistancebetweentheLVDSoutput(LVDSinterface) 100 Ω
L
T Operatingfree-airtemperature –40 85 °C
A
(1) SeeTheoryofOperationintheapplicationsection.
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ELECTRICAL CHARACTERISTICS(1)
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,samplingfrequency=200MSPS,50%clockdutycycle,–1dBFS
differentialanaloginput,internalreferencemode,LVDSandCMOSinterfacesunlessotherwisenoted.
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V
MIN MAX
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Resolution 11 bits
ANALOGINPUTS
Differentialinputvoltagerange 2.0 V
PP
Differentialinputresistance(atdc) SeeFigure44 >1 MΩ
Differentialinputcapacitance SeeFigure45 3.5 pF
Analoginputbandwidth 700 MHz
Analoginputcommonmodecurrent(perchannel) 3.6 m A/MSPS
VCMcommonmodevoltageoutput 1.5 V
VCMoutputcurrentcapability ±4 mA
POWERSUPPLY
IAVDD Analogsupplycurrent 262 mA
IDRVDD OutputbuffersupplycurrentLVDSinterface With100Ωexternal 120 mA
termination
IDRVDD OutputbuffersupplycurrentCMOSinterface Noexternalload 87 mA
capacitance
Analogpower 865 1025 mW
DigitalpowerLVDSinterface 216 306 mW
Globalpowerdown 45 75 mW
Nomissingcodes Assured
DCACCURACY
DNL DifferentialNon-Linearity Fin=170MHz -0.6 ±0.2 0.6 LSB
INL IntegralNon-Linearity Fin=170MHz -2.5 ±0.75 2.5 LSB
OffsetError -20 ±2 20 mV
Offseterrortemperaturecoefficient 0.02 mV/C
Offseterrorvariationwithsupply 0.5 mV/V
Therearetwosourcesofgainerror–internalreferenceinaccuracyandchannelgainerror
Gainerrorduetointernalreferenceinaccuracyalone -1 ±0.2 1 %FS
Gainerrorofchannelalone(2) -1 +0.2 1 %FS
Channelgainerrortemperaturecoefficient 0.002 Δ%/°C
Differenceingainerrors
betweentwochannels -2 2
withinthesamedevice
Gainmatching(3) %FS
Differenceingainerrors
betweentwochannels -4 4
acrosstwodevices
(1) InCMOSinterface,theDRVDDcurrentscaleswiththesamplingfrequencyandtheloadcapacitanceonoutputpins.
(2) Thisisspecifiedbydesignandcharacterization;itisnottestedinproduction.
(3) Fortwochannelswithinthesamedevice,onlythechannelgainerrormatters,asthereferenceiscommonforbothchannels.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,samplingfrequency=200MSPS,50%clockdutycycle,–1dBFS
differentialanaloginput,internalreferencemode,SNRBoostdisabled,LVDSandCMOSinterfacesunlessotherwisenoted.
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V
MIN MAX
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
SNR Fin=20MHz 67
Signaltonoiseratio Fin=70MHz 66.8
LVDS dBFS
Fin=170MHz 0dBgain 64.5 66.3
6dBgain 64.4
Table1.SNREnhancementWithSNRBoostEnabled
SNRBoostbath-tubcenteredatFsx0.25,–1dBFSinputappliedatFin=125MHz,Samplingfrequency=200MSPS
SNRWithinSpecifiedbandwidth,dBFS
Bandwidth,MHz InDefaultMode(SNRBoostDisabled) WithSNRBoostEnabled(1)
MIN TYP MAX MIN TYP MAX
5 78.8 79.6 83 85.6
10 75.8 76.6 80 82.6
15 74 74.9 78.2 80.9
20 72.7 73.6 77 79.6
30 71 71.9 74.4 76.4
40 69.8 70.6 72.7 74.5
(1) UsingrecommendedSNRBoostcoefficients.SeenoteonSNRBoostinapplicationsection.
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ELECTRICAL CHARACTERISTICS
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,samplingfrequency=200MSPS,50%clockdutycycle,–1dBFS
differentialanaloginput,internalreferencemode,SNRBoostdisabled,0dBgain,LVDSandCMOSinterfacesunless
otherwisenoted.
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V
MIN MAX
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Fin=20MHz 66.9
SINAD Fin=70MHz 66.6
dBFS
SignaltoNoiseandDistortionRatio 0dBgain 63.5 65.7
Fin=170MHz
6dBgain 64.2
Fin=20MHz 85
SFDR Fin=70MHz 83
dBc
SpuriousFreeDynamicRange 0dBgain 73 78
Fin=170MHz
6dBgain 81
Fin=20MHz 83
THD Fin=70MHz 81
dBc
TotalHarmonicDistortion 0dBgain 71.5 75.5
Fin=170MHz
6dBgain 79
Fin=20MHz 94
HD2 Fin=70MHz 90
dBc
SecondHarmonicDistortion 0dBgain 73 83
Fin=170MHz
6dBgain 92
Fin=20MHz 85
HD3 Fin=70MHz 83
dBc
ThirdHarmonicDistortion 0dBgain 73 78
Fin=170MHz
6dBgain 81
Fin=20MHz 94
WorstSpur
Fin=70MHz 92 dBc
Otherthansecond,thirdharmonics
Fin=170MHz 80 90
IMD
F1=185MHz,F2=190MHz,Eachtoneat–7dBFS 87 dBFS
2-ToneInter-modulationDistortion
Recoverytowithin1%(offinalvalue)for6-dBoverloadwith 1 clock
InputOverloadrecovery
sinewaveinputatFclk/4 cycles
Cross-talk Upto200MHzcross-talkfrequency 90 dB
PSRR
For100mVppsignalonAVDDsupply 25 dB
ACPowerSupplyRejectionRatio
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DIGITAL CHARACTERISTICS — ADS62C17
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1.AVDD=3.3V,DRVDD=1.8V
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUTS–CTRL1,CTRL2,CTRL3,RESET,SCLK,SDATA,SEN (1)
High-levelinputvoltage Alldigitalinputssupport1.8Vand3.3VCMOS 1.3
V
Low-levelinputvoltage logiclevels. 0.4
SDATA,SCLK(2) V =3.3V 16
High-levelinputcurrent HIGH m A
SEN(3) V =3.3V 10
HIGH
SDATA,SCLK V =0V 0
Low-levelinputcurrent LOW m A
SEN V =0V –20
LOW
Inputcapacitance 4 pF
DIGITALOUTPUTS–CMOSINTERFACE(DA0-DA10,DB0-DB10,CLKOUT,SDOUT)
Ioh=1mA DRVDD– DRVDD
High-leveloutputvoltage V
0.1
Low-leveloutputvoltage Iol=1mA 0 0.1 V
Outputcapacitance(internaltodevice) 2 pF
DIGITALOUTPUTS–LVDSINTERFACE(DA0P/MTODA10P/M,DB0P/MTODB10P/M,CLKOUTP/M)
VODH,High-leveloutputdifferentialvoltage Withexternal100Ωtermination +275 +350 +425 mV
VODL,Low-leveloutputdifferentialvoltage Withexternal100Ωtermination. –425 –350 –275 mV
VOCM,Outputcommon-modevoltage 1.0 1.15 1.40 V
Capacitanceinsidethedevicefromeachoutput 2 pF
OutputCapacitance
toground
(1) SCLK,SDATA,SENfunctionasdigitalinputpinsinserialconfigurationmode.
(2) SDATA,SCLKhaveinternal200kΩpull-downresistor
(3) SENhasinternal100kΩpull-upresistortoAVDD.
DAnP/ DBnP
Logic 0 Logic 1
VODL= -350 mV* VODH= +350 mV*
DAnM / DBnM
V
OCM
GNGDND
* With external 100Wtermination
Figure2. LVDSOutput VoltageLevels
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TIMING CHARACTERISTICS — LVDS AND CMOS MODES(1)
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,samplingfrequency=200MSPS,sinewaveinputclock,C =
LOAD
5pF(2),R =100Ω(3),nointernaltermination,LOWSPEEDmodedisabled,unlessotherwisenoted.
LOAD
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.7Vto
MIN MAX
1.9V.
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
ta Aperturedelay 0.7 1.2 1.7 ns
Aperturedelaymatching betweentwochannelsofthesamedevice ±50 ps
tj Aperturejitter 145 fsrms
TimetovaliddataaftercomingoutofSTANDBYmode 1 3
m s
Wake-uptime Timetovaliddataaftercomingoutofglobalpowerdown 20 50
Timetovaliddataafterstoppingandrestartingtheinputclock 10 Clock
ADCLatency(4) Default,afterreset 22 cycles
DDRLVDSMODE(5)
tsu Datasetuptime(6) Datavalid(7)tozero-crossingofCLKOUTP 0.8 1.15 ns
th Dataholdtime(7) Zero-crossingofCLKOUTPtodatabecominginvalid(7) 0.8 1.15 ns
tPDI Clockpropagationdelay Inputclockfallingedgecross-overtooutputclockrisingedge tPDI=0.69×Ts+tdelay
cross-over
tdelay 100MSPS≤Samplingfrequency≤200MSPS 4.2 5.7 7.2 ns
Ts=1/Samplingfrequency
tdelayskew Dteimffepreernactuerein&tdeSlaVyDbDetwsuepepnlytwvooldtaegveic.esoperatingatsame ±500 ps
Dutycycleofdifferentialclock,(CLKOUTP-CLKOUTM)
LVDSbitclockdutycycle 52%
100MSPS≤Samplingfrequency≤200MSPS
Risetimemeasuredfrom–100mVto+100mV
tRISE,tFALL Datarisetime,Datafalltime Falltimemeasuredfrom+100mVto–100mV 0.14 ns
1MSPS≤Samplingfrequency≤200MSPS
Risetimemeasuredfrom–100mVto+100mV
tCLKRISE, Outputclockrisetime, Falltimemeasuredfrom+100mVto–100mV 0.14 ns
tCLKFALL Outputclockfalltime 1MSPS≤Samplingfrequency≤200MSPS
tOE Outputbufferenabletodatadelay Timetovaliddataafteroutputbufferbecomesactive 100 ns
PARALLELCMOSMODEatFs=200MSPS(8)
tSTART Inputclocktodatadelay Inputclockfallingedgecross-overtostartofdatavalid(7) 2.5 ns
tDV Datavalidtime Timeintervalofvaliddata(7) 1.7 2.7 ns
tPDI Clockpropagationdelay Inputclockfallingedgecross-overtooutputclockrisingedge tPDI=0.28×Ts+tdelay
cross-over
tdelay 100MSPS≤Samplingfrequency≤150MSPS 5.5 7.5 8.5 ns
Ts=1/Samplingfrequency
Dutycycleofoutputclock,CLKOUT
Outputclockdutycycle 43
100MSPS≤Samplingfrequency≤150MSPS
Risetimemeasuredfrom20%to80%ofDRVDD
tRISE,tFALL Datarisetime,Datafalltime Falltimemeasuredfrom80%to20%ofDRVDD 1.2 ns
1≤Samplingfrequency≤200MSPS
Risetimemeasuredfrom20%to80%ofDRVDD
tCLKRISE, Outputclockrisetime, Falltimemeasuredfrom80%to20%ofDRVDD 0.8 ns
tCLKFALL Outputclockfalltime 1≤Samplingfrequency≤150MSPS
Outputbufferenable(OE)todata
tOE delay Timetovaliddataafteroutputbufferbecomesactive 100 ns
(1) Timingparametersareensuredbydesignandcharacterizationandnottestedinproduction.
(2) C istheeffectiveexternalsingle-endedloadcapacitancebetweeneachoutputpinandground
LOAD
(3) R isthedifferentialloadresistancebetweentheLVDSoutputpair.
LOAD
(4) Athigherfrequencies,t isgreaterthanoneclockperiodandoveralllatency=ADClatency+1.
PDI
(5) Measurementsaredonewithatransmissionlineof100Ωcharacteristicimpedancebetweenthedeviceandtheload.
Setupandholdtimespecificationstakeintoaccounttheeffectofjitterontheoutputdataandclock.
(6) DatavalidreferstoLOGICHIGHof+100.0mVandLOGICLOWof-100.0mV.
(7) DatavalidreferstoLOGICHIGHof1.26VandLOGICLOWof0.54V.
(8) ForFs>150MSPS,itisrecommendedtouseexternalclockfordatacaptureandNOTthedeviceoutputclocksignal(CLKOUT).
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Table2.LVDSTimingsatLower SamplingFrequencies
SetupTime,ns HoldTime,ns
SamplingFrequency,MSPS
MIN TYP MAX MIN TYP MAX
185 0.9 1.25 0.85 1.25
150 1.15 1.6 1.1 1.5
125 1.6 2 1.45 1.85
<100EnableLOWSPEEDmode 2 2
t ,ns
PDI
1≤Fs≤100EnableLOWSPEEDmode MIN TYP MAX
12.6
Table3.CMOSTimingsatLower SamplingFrequencies
TimingsSpecifiedWithRespecttoInputClock
SamplingFrequency,MSPS t ,ns DataValidTime,ns
START
MIN TYP MAX MIN TYP MAX
190 1.9 2 3
170 0.9 2.7 3.7
150 6 3.6 4.6
TimingsSpecifiedWithRespecttoCLKOUT
SamplingFrequency,MSPS SetupTime,ns HoldTime,ns
MIN TYP MAX MIN TYP MAX
150 2.8 4.4 0.5 1.2
125 3.8 5.4 0.8 1.5
<100EnableLOWSPEEDmode 5 1.2
t ,ns
PDI
1≤Fs≤100EnableLOWSPEEDmode MIN TYP MAX
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