Dual, 1MSPS, 16-/14-/12-Bit, 4x2 or 2x2 Channel, Simultaneous Sampling ADCs

51 Pages·2015·1.35 MB·English

ADS8363
ADS7263
ADS7223
www.ti.com SBAS523B–OCTOBER2010–REVISEDJANUARY2011
Dual, 1MSPS, 16-/14-/12-Bit, 4×2 or 2×2 Channel, Simultaneous Sampling
Analog-to-Digital Converter
CheckforSamples:ADS8363,ADS7263,ADS7223
FEATURES DESCRIPTION
1
• EightPseudo-orFour Fully-DifferentialInputs The ADS8363 is a dual, 16-bit, 1MSPS
2
• SimultaneousSamplingofTwoChannels analog-to-digital converter (ADC) with eight pseudo-
or four fully-differential input channels grouped into
• ExcellentACPerformance:
two pairs for simultaneous signal acquisition. The
– SNR:
analog inputs are maintained differentially to the input
93dB(ADS8363) of the ADC. The input multiplexer can be used in
85dB(ADS7263) either pseudo-differential mode, supporting up to four
73dB(ADS7223) channels per ADC (4x2), or in fully-differential mode
– THD: that allows to convert up to two inputs per ADC (2x2).
The ADS7263 is a 14-bit version while the ADS7223
–98dB(ADS8363)
isa12-bitversionoftheADS8363.
–92dB(ADS7263)
–86dB(ADS7223) The ADS8363/7263/7223 offer two programmable
reference outputs, flexible supply voltage ranges, a
• DualProgrammableand Buffered2.5V
programmable auto-sequencer, data storage of up to
ReferenceAllows:
four conversion results per channel, and several
– TwoDifferentInputVoltageRangeSettings
power-downfeatures.
– Two-LevelPGA Implementation
Alldevicesareofferedina5x5mmQFN-32package.
• ProgrammableAuto-Sequencer
• IntegratedDataStorage(up to4per channel)
Functional BlockDiagram
forOversamplingApplications
AVDD DVDD
• 2-BitCounter forSafetyApplications
• FullySpecifiedover theExtendedIndustrial
CHA1P/CHA3
TemperatureRange CHA1N/CHA2
Input
CHA0P/CHA1 SAR ADC CS
Mux
CHA0N/CHA0 CLOCK
APPLICATIONS CMA Serial BUSY
REF1 Interface
• MotorControl:Currentand Position SDI
REF2 and
MeasurementincludingSafetyApplications CHB1P/CHB3 FIFO RD
• PowerQualityMeasurement CHB1N/CHB2 SDOA
Input
CHB0P/CHB1 SAR ADC SDOB
• Three-PhasePowerControl CHB0N/CHB0 Mux
• ProgrammableLogicControllers CMB
• IndustrialAutomation REF1
M0
• ProtectionRelays REFIO1 String 2.5V Control M1
DAC REF Logic
REF2 CONVST
String
REFIO2
DAC
RGND AGND DGND
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
Alltrademarksarethepropertyoftheirrespectiveowners.
2
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2011,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS8363
ADS7263
ADS7223
SBAS523B–OCTOBER2010–REVISEDJANUARY2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document,orvisitthedeviceproductfolderatwww.ti.com.
FAMILYOVERVIEW
PRODUCT RESOLUTION NMC INL SNR THD
ADS8363 16bits 16or15bits(1) ±3or±4LSB(1) 93dB(typ) –98dB(typ)
ADS7263 14bits 14bits ±1LSB 85dB(typ) –92dB(typ)
ADS7223 12bits 12bits ±0.5LSB 73dB(typ) –86dB(typ)
(1) SeeElectricalCharacteristics.
ABSOLUTE MAXIMUM RATINGS(1)
Overoperatingfree-airtemperaturerange,unlessotherwisenoted.
ADS8363,ADS7263,ADS7223 UNIT
Supplyvoltage,AVDDtoAGNDorDVDDtoDGND –0.3to+6 V
Supplyvoltage,DVDDtoAVDD 1.2×AVDD(2) V
AnalogandreferenceinputvoltagewithrespecttoAGND AGND–0.3toAVDD+0.3 V
DigitalinputvoltagewithrespecttoDGND DGND–0.3toDVDD+0.3 V
Groundvoltagedifference|AGND-DGND| 0.3 V
Inputcurrenttoanypinexceptsupplypins –10to+10 mA
Maximumvirtualjunctiontemperature,TJ +150 °C
Humanbodymodel(HBM),
Electrostatic JEDECstandard22,testmethodA114-C.01 ±2000 V
discharge(ESD)
ratings,allpins Chargeddevicemodel(CDM), ±500 V
JEDECstandard22,testmethodC101
(1) Stressesabovetheseratingsmaycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthe
deviceattheseoranyotherconditionsbeyondthosespecifiedisnotimplied.Exposuretoabsolutemaximumconditionsforextended
periodsmayaffectdevicereliability.
(2) ExceedingthespecifiedlimitcausesanincreaseoftheDVDDleakagecurrentandleadstomalfunctionofthedevice.
THERMAL INFORMATION
ADS8363,
ADS7263,
THERMALMETRIC(1) ADS7223 UNITS
RHB
32PINS
q Junction-to-ambientthermalresistance 33.3
JA
q Junction-to-case(top)thermalresistance 29.5
JCtop
q Junction-to-boardthermalresistance 7.3
JB
°C/W
y Junction-to-topcharacterizationparameter 0.2
JT
y Junction-to-boardcharacterizationparameter 7.4
JB
q Junction-to-case(bottom)thermalresistance 0.9
JCbot
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
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ELECTRICAL CHARACTERISTICS: ADS8363
Allminimum/maximumspecificationsatT =–40°Cto+125°C,specifiedsupplyvoltagerange,VREF=2.5V(int),andt =
A DATA
1MSPS,unlessotherwisenoted.TypicalvaluesareatT =+25°C,AVDD=5V,andDVDD=3.3V.
A
ADS8363
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
RESOLUTION 16 Bits
DCACCURACY
Half-clockmode –3 ±1.2 +3 LSB
INL Integralnonlinearity
Full-clockmode –4 ±1.5 +4 LSB
Half-clockmode –0.99 ±0.6 +2 LSB
DNL Differentialnonlinearity
Full-clockmode –1.5 ±0.8 +3 LSB
V Inputoffseterror –2 ±0.2 +2 mV
OS
V match ADCtoADC –1 ±0.1 +1 mV
OS
dV /dT Inputoffsetthermaldrift 1 mV/°C
OS
Referencedtothevoltageat
G Gainerror –0.1 ±0.01 +0.1 %
ERR REFIOx
G match ADCtoADC –0.1 ±0.005 +0.1 %
ERR
Referencedtothevoltageat
G /dT Gainerrorthermaldrift 1 ppm/°C
ERR REFIOx
CMRR Common-moderejectionratio BothADCs,dcto100kHz 92 dB
ACACCURACY
SINAD Signal-to-noise+distortion V =5V at10kHz 89 92 dB
IN PP
SNR Signal-to-noiseratio V =5V at10kHz 90 93 dB
IN PP
THD Totalharmonicdistortion V =5V at10kHz –98 –90 dB
IN PP
SFDR Spurious-freedynamicrange V =5V at10kHz 90 100 dB
IN PP
ELECTRICAL CHARACTERISTICS: ADS7263
Allminimum/maximumspecificationsatT =–40°Cto+125°C,specifiedsupplyvoltagerange,VREF=2.5V(int),andt =
A DATA
1MSPS,unlessotherwisenoted.TypicalvaluesareatT =+25°C,AVDD=5V,andDVDD=3.3V.
A
ADS7263
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
RESOLUTION 14 Bits
DCACCURACY
INL Integralnonlinearity –1 ±0.4 +1 LSB
DNL Differentialnonlinearity –0.5 ±0.2 +1 LSB
V Inputoffseterror –2 ±0.2 +2 mV
OS
V match ADCtoADC –1 ±0.1 +1 mV
OS
dV /dT Inputoffsetthermaldrift 1 mV/°C
OS
Referencedtothevoltageat
G Gainerror –0.1 ±0.01 +0.1 %
ERR REFIOx
G match ADCtoADC –0.1 ±0.005 +0.1 %
ERR
Referencedtothevoltageat
G /dT Gainerrorthermaldrift 1 ppm/°C
ERR REFIOx
CMRR Common-moderejectionratio BothADCs,dcto100kHz 92 dB
ACACCURACY
SINAD Signal-to-noise+distortion V =5V at10kHz 82 84 dB
IN PP
SNR Signal-to-noiseratio V =5V at10kHz 84 85 dB
IN PP
THD Totalharmonicdistortion V =5V at10kHz –92 –88 dB
IN PP
SFDR Spurious-freedynamicrange V =5V at10kHz 88 92 dB
IN PP
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ELECTRICAL CHARACTERISTICS: ADS7223
Allminimum/maximumspecificationsatT =–40°Cto+125°C,specifiedsupplyvoltagerange,VREF=2.5V(int),andt =
A DATA
1MSPS,unlessotherwisenoted.TypicalvaluesareatT =+25°C,AVDD=5V,andDVDD=3.3V.
A
ADS7223
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
RESOLUTION 12 Bits
DCACCURACY
INL Integralnonlinearity –0.5 ±0.2 +0.5 LSB
DNL Differentialnonlinearity –0.5 ±0.1 +0.5 LSB
V Inputoffseterror –2 ±0.2 +2 mV
OS
V match ADCtoADC –1 ±0.1 +1 mV
OS
dV /dT Inputoffsetthermaldrift 1 mV/°C
OS
Referencedtothevoltageat
G Gainerror –0.1 ±0.01 +0.1 %
ERR REFIOx
G match ADCtoADC –0.1 ±0.005 +0.1 %
ERR
Referencedtothevoltageat
G /dT Gainerrorthermaldrift 1 ppm/°C
ERR REFIOx
CMRR Common-moderejectionratio BothADCs,dcto100kHz 92 dB
ACACCURACY
SINAD Signal-to-noise+distortion V =5V at10kHz 71 72 dB
IN PP
SNR Signal-to-noiseratio V =5V at10kHz 72 73 dB
IN PP
THD Totalharmonicdistortion V =5V at10kHz –86 –84 dB
IN PP
SFDR Spurious-freedynamicrange V =5V at10kHz 84 86 dB
IN PP
ELECTRICAL CHARACTERISTICS: GENERAL
Allminimum/maximumspecificationsatT =–40°Cto+125°C,specifiedsupplyvoltagerange,VREF=2.5V(int),andt =
A DATA
1MSPS,unlessotherwisenoted.TypicalvaluesareatT =+25°C,AVDD=5V,andDVDD=3.3V.
A
ADS8363,ADS7263,ADS7223
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
ANALOGINPUT
(CHxxP–CHxxN)orCHxxto
FSR Full-scaleinputrange –V +V V
CMx REF REF
V Absoluteinputvoltage CHxxxtoAGND –0.1 AVDD+0.1 V
IN
C Inputcapacitance CHxxxtoAGND 45 pF
IN
C Differentialinputcapacitance 22.5 pF
ID
I Inputleakagecurrent –16 16 nA
IL
PSRR Power-supplyrejectionratio AVDD=5.5V 75 dB
SAMPLINGDYNAMICS
Half-clockmode 17.5 t
CLK
t ConversiontimeperADC
CONV
Full-clockmode 35 t
CLK
Half-clockmode 2 t
CLK
t Acquisitiontime
ACQ
Full-clockMode 4 t
CLK
f Datarate 25 1000 kSPS
DATA
t Aperturedelay 6 ns
A
t match ADCtoADC 50 ps
A
t Aperturejitter 50 ps
AJIT
Half-clockmode 0.5 20 MHz
f Clockfrequency
CLK
Full-clockmode 1 40 MHz
Half-clockmode 50 2000 ns
t Clockperiod
CLK
Full-clockmode 25 1000 ns
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ELECTRICAL CHARACTERISTICS: GENERAL (continued)
Allminimum/maximumspecificationsatT =–40°Cto+125°C,specifiedsupplyvoltagerange,VREF=2.5V(int),andt =
A DATA
1MSPS,unlessotherwisenoted.TypicalvaluesareatT =+25°C,AVDD=5V,andDVDD=3.3V.
A
ADS8363,ADS7263,ADS7223
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
INTERNALVOLTAGEREFERENCE
Resolution ReferenceoutputDACresolution 10 Bits
Over20%to100%DACrange 0.2V V V
REFOUT REFOUT
V Referenceoutputvoltage REFIO1,DAC=3FFh, 2.485 2.500 2.515 V
REFOUT
REFIO2,DAC=3FFh 2.480 2.500 2.520 V
dV /dT Referencevoltagedrift ±10 ppm/°C
REFOUT
DNL DACdifferentiallinearityerror –4 ±1 4 LSB
DAC
INL DACintegrallinearityerror –4 ±0.5 4 LSB
DAC
V DACoffseterror V =0.5V –4 ±1 4 LSB
OSDAC REFOUT
PSRR Power-supplyrejectionratio 73 dB
I Referenceoutputdccurrent –2 +2 mA
REFOUT
Referenceoutputshort-circuit
IREFSC current(1) 50 mA
t Referenceoutputsettlingtime C =22mF 8 ms
REFON REF
VOLTAGEREFERENCEINPUT
V Referenceinputvoltagerange 0.5 2.5 2.525 V
REF
I Referenceinputcurrent 50 mA
REF
Externalceramicreference
C 22 mF
REF capacitance
DIGITALINPUTS(2)
I Inputcurrent V =DVDDtoDGND –50 +50 nA
IN IN
C Inputcapacitance 5 pF
IN
Logicfamily CMOSwithSchmitt-Trigger
V High-levelinputvoltage DVDD=4.5Vto5.5V 0.7DVDD DVDD+0.3 V
IH
V Low-levelinputvoltage DVDD=4.5Vto5.5V –0.3 0.3DVDD V
IL
Logicfamily LVCMOS
V High-levelinputvoltage DVDD=2.3Vto3.6V 2 DVDD+0.3 V
IH
V Low-levelinputvoltage DVDD=2.3Vto3.6V –0.3 0.8 V
IL
DIGITALOUTPUTS(2)V
C Outputcapacitance 5 pF
OUT
C Loadcapacitance 30 pF
LOAD
Logicfamily CMOS
V High-leveloutputvoltage DVDD=4.5V,I =–100µA 4.44 V
OH OH
V Low-leveloutputvoltage DVDD=4.5V,I =+100µA 0.5 V
OL OH
Logicfamily LVCMOS
V High-leveloutputvoltage DVDD=2.3V,I =–100µA DVDD–0.2 V
OH OH
V Low-leveloutputvoltage DVDD=2.3V,I =+100µA 0.2 V
OL OH
(1) Referenceoutputcurrentisnotinternallylimited.
(2) Specifiedbydesign;notproductiontested.
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ELECTRICAL CHARACTERISTICS: GENERAL (continued)
Allminimum/maximumspecificationsatT =–40°Cto+125°C,specifiedsupplyvoltagerange,VREF=2.5V(int),andt =
A DATA
1MSPS,unlessotherwisenoted.TypicalvaluesareatT =+25°C,AVDD=5V,andDVDD=3.3V.
A
ADS8363,ADS7263,ADS7223
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
POWERSUPPLY
AVDDtoAGND,half-clockmode 2.7 5.0 5.5 V
AVDD Analogsupplyvoltage
AVDDtoAGND,full-clockmode 4.5 5.0 5.5 V
3Vand3.3Vlevels 2.3 2.5 3.6 V
DVDD Digitalsupplyvoltage
5Vlevels,half-clockmodeonly 4.5 5.0 5.5 V
AVDD=3.6V 12.0 16.0 mA
AVDD=5.5V 15.0 20.0 mA
AVDD=3.6V,sleep/auto-sleep
0.8 1.2 mA
AIDD Analogsupplycurrent modes
AVDD=5.5V,sleep/auto-sleep
0.9 1.4 mA
modes
Power-downmode 0.005 mA
DVDD=3.6V,C =10pF 1.1 2.5 mA
LOAD
DIDD Digitalsupplycurrent
DVDD=5.5V,C =10pF 3 6 mA
LOAD
Powerdissipation(normal AVDD=DVDD=3.6V 47.2 66.6 mW
P
D operation) AVDD=5.5V,DVDD=3.6V 86.5 117.0 mW
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PIN CONFIGURATION
RHBPACKAGE
QFN-32
(TOPVIEW)
D D D D A
B A N D N D O
M M G V G V C D
C C A A D D N S
32 31 30 29 28 27 26 25
CHB1P/CHB3 1 24 SDOB
CHB1N/CHB2 2 23 BUSY
CHB0P/CHB1 3 22 CLOCK
ADS8363
CHB0N/CHB0 4 21 CS
ADS7263
CHA1P/CHA3 5 ADS7223 20 RD
CHA1N/CHA2 6 19 CONVST
CHA0P/CHA1 7 18 SDI
(Thermal Pad)
CHA0N/CHA0 8 17 M0
9 10 11 12 13 14 15 16
1 2 D D D C C 1
O O N N D N N M
FI FI G G V
E E R A A
R R
PinDescriptions
PIN
NAME NO. TYPE(1) DESCRIPTION
CHB1P/CHB3 1 AI Fully-differentialnoninvertinganaloginputchannelB1orpseudo-differentialinputB3
CHB1N/CHB2 2 AI Fully-differentialinvertinganaloginputchannelB1orpseudo-differentialinputB2
CHB0P/CHB1 3 AI Fully-differentialnoninvertinganaloginputchannelB0orpseudo-differentialinputB1
CHB0N/CHB0 4 AI Fully-differentialinvertinganaloginputchannelB0orpseudo-differentialinputB0
CHA1P/CHA3 5 AI Fully-differentialnoninvertinganaloginputchannelA1orpseudo-differentialinputA3
CHA1N/CHA2 6 AI Fully-differentialinvertinganaloginputchannelA1orpseudo-differentialinputA2
CHA0P/CHA1 7 AI Fully-differentialnonInvertinganaloginputchannelA1orpseudo-differentialinputA1
CHA0N/CHA0 8 AI Fully-differentialinvertinganaloginputchannelA1orpseudo-differentialinputA0
REFIO1 9 AIO Referencevoltageinput/output1.Aceramiccapacitorof22µFconnectedtoRGNDisrequired.
REFIO2 10 AIO Referencevoltageinput/output2.Aceramiccapacitorof22µFconnectedtoRGNDisrequired.
RGND 11 P Referenceground.Connecttoanaloggroundplanewithadedicatedvia.
AGND 12,30 P Analogground.Connecttoanaloggroundplane.
AVDD 13,29 P Analogpowersupply,2.7Vto5.5V.DecoupletoAGNDwitha1mFceramiccapacitor.
14,
NC NC Thispinisnotinternallyconnected.
15,26
M1 16 DI Modepin1.Selectsthedigitaloutputmode(seeTable4).
M0 17 DI Modepin0.Selectsanaloginputchannelmode(seeTable4).
Serialdatainput.Thispinisusedtosetupoftheinternalregisters,andcanalsobeusedin
SDI 18 DI
ADS8361-compatiblemanner.ThedataonSDIareignoredwhenCSishigh.
Conversionstart.TheADCswitchesfromsampleintoholdmodeontherisingedgeofCONVST.
CONVST 19 DI
Thereafter,theconversionstartswiththenextrisingedgeoftheCLOCKpin.
Readdata.SynchronizationpulsefortheSDOxoutputsandSDIinput.RDonlytriggerswhenCSis
RD 20 DI
low.
(1) AI=analoginput,AIO=analoginput/output,DI=digitalinput,DO=digitaloutput,DIO=digitalinput/output,P=powersupply,NC=
notconnected.
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PinDescriptions(continued)
PIN
NAME NO. TYPE(1) DESCRIPTION
Chipselect.Whenthispinislow,theSDOx,SDI,andRDpinsareactive;whenthispinishigh,the
CS 21 DI
SDOxoutputsare3-stated,whiletheSDIandRDinputsareignored.
Externalclockinput.Therangeis0.5MHzto20MHzinhalf-clockmode,or1MHzto40MHzin
CLOCK 22 DI
full-clockmode.
Converterbusyindicator.BUSYgoeshighwhentheinputsareinholdmodeandreturnstolowafter
BUSY 23 DO
theconversioniscomplete.
SDOB 24 DO SerialdataoutputforconverterB.ActiveonlyifM1islow.3-statewhenCSishigh.
SDOA 25 DO SerialdataoutputforconverterA.3-statewhenCSishigh.
DVDD 27 P Digitalsupply,2.3Vto5.5V.DecoupletoDGNDwitha1mFceramiccapacitor.
DGND 28 P Digitalground.Connecttodigitalgroundplane.
CMA 31 AI Common-modevoltageinputforchannelsAx(inpseudo-differentialmodeonly).
CMB 32 AI Common-modevoltageinputforchannelsBx(inpseudo-differentialmodeonly).
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TIMING DIAGRAMS
tCLK
1 tCLKL tCLKH 18 21
CLOCK
tCONV tACQ
CS
t1
t2
CONVST
tDATA
tD1 tD2
BUSY conversion n
tH1
t3 tS1
RD
tD5 data n-1 tH3 tD3 tD6
SDOx(1) CH AD CH
MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(CID =‘0’) 0/1 A/B 0/1
data n-1
SDOx(1)
(CID =‘1’) MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB
tS2 tH2
SDI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15
(1) TheADS7263/7223outputdatawiththeMSBlocatedasADS8363andlast2/4bitsbeing'0'.
Figure1. DetailedTimingDiagram:Half-ClockMode(ADS8361-Compatible)
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TIMING DIAGRAMS (continued)
1 tCLK tCLKL tCLKH 23 25 36 41
CLOCK
tCONV tACQ
CS
tDATA
t1
t2
CONVST
tD1 tD2
BUSY conversion n
tH1
tS1
RD
tD5 tH4 data n tD4 tD6
(CID =‘0’) SDOx(1) C0/H1AA/DB MBS 1D4 1D3 1D2 1D1 1D0 D9 D8 D7 D6 D5 D4 D3 D0 D1 D0
tS2 tH2
SDI 1D5 1D4 1D3 1D2 1D1 1D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RD
tD5 tH4 data n tD4
(CID =‘1’) SDOx(1) MBS 1D4 1D3 1D2 1D1 1D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tS2 tH2
SDI 1D5 1D4 1D3 1D2 1D1 1D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(2) TheADS7263/7223outputdatawiththeMSBlocatedasADS8363andlast2/4bitsbeing'0'.
Figure2. DetailedTimingDiagram: Full-Clock Mode
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